Searched refs:ShiftRHS (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 5271 const SDValue ShiftRHS = RHS.getOperand(1); in SelectSVERegRegAddrMode() local
5272 if (auto *C = dyn_cast<ConstantSDNode>(ShiftRHS)) in SelectSVERegRegAddrMode()
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| H A D | AArch64ISelLowering.cpp | 14636 uint32_t ShiftRHS = 0; in tryCombineToEXTR() local
14638 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi)) in tryCombineToEXTR()
14646 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) in tryCombineToEXTR()
14651 std::swap(ShiftLHS, ShiftRHS); in tryCombineToEXTR()
14655 DAG.getConstant(ShiftRHS, DL, MVT::i64)); in tryCombineToEXTR()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6539 MachineOperand &ShiftRHS = ShiftInst->getOperand(2); in selectShiftedRegister() local
6540 auto Immed = getImmedFromMO(ShiftRHS); in selectShiftedRegister()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 30743 unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL; in LowerRotate() local
30757 DAG.getNode(ShiftRHS, DL, VT, R, DAG.getConstant(4, DL, VT))); in LowerRotate()
30767 DAG.getNode(ShiftRHS, DL, VT, R, DAG.getConstant(6, DL, VT))); in LowerRotate()
30777 DAG.getNode(ShiftRHS, DL, VT, R, DAG.getConstant(7, DL, VT))); in LowerRotate()
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