Searched refs:ShiftR (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/include/llvm/Support/ |
| H A D | ScaledNumber.h | 310 int32_t ShiftR = ScaleDiff - ShiftL; in matchScales() local
311 if (ShiftR >= getWidth<DigitsT>()) { in matchScales()
318 RDigits >>= ShiftR; in matchScales()
321 RScale += ShiftR; in matchScales()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 1290 int ShiftR = SMA.MinSrc; in packs() local
1291 if (ShiftR >= static_cast<int>(HwLen)) { in packs()
1294 ShiftR -= HwLen; in packs()
1296 OpRef RetVal = valign(Va, Vb, ShiftR, Ty, Results); in packs()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 3558 SDValue ShiftR = in get64BitZExtCompare() local
3565 ShiftR, ShiftL, SubtractCarry), 0); in get64BitZExtCompare()
3713 SDValue ShiftR = in get64BitSExtCompare() local
3725 ShiftR, ShiftL, SubtractCarry), 0); in get64BitSExtCompare()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1948 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); in widenScalarAddSubShlSat() local
1951 {ShiftL, ShiftR}, MI.getFlags()); in widenScalarAddSubShlSat()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 21915 SDValue ShiftR = Op->getOperand(0); in SimplifyDemandedBitsForTargetNode() local
21916 if (ShiftR->getOpcode() != AArch64ISD::VLSHR) in SimplifyDemandedBitsForTargetNode()
21919 if (!ShiftL.hasOneUse() || !ShiftR.hasOneUse()) in SimplifyDemandedBitsForTargetNode()
21923 unsigned ShiftRBits = ShiftR->getConstantOperandVal(1); in SimplifyDemandedBitsForTargetNode()
21941 return TLO.CombineTo(Op, ShiftR->getOperand(0)); in SimplifyDemandedBitsForTargetNode()
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