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Searched refs:ShiftOffset (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp69 unsigned ShiftOffset; member
265 unsigned ShiftOffset = 8 * Offset; in matchCvtF32UByteN() local
267 ShiftOffset += ShiftAmt; in matchCvtF32UByteN()
269 ShiftOffset -= ShiftAmt; in matchCvtF32UByteN()
272 MatchInfo.ShiftOffset = ShiftOffset; in matchCvtF32UByteN()
273 return ShiftOffset < 32 && ShiftOffset >= 8 && (ShiftOffset % 8) == 0; in matchCvtF32UByteN()
283 unsigned NewOpc = AMDGPU::G_AMDGPU_CVT_F32_UBYTE0 + MatchInfo.ShiftOffset / 8; in applyCvtF32UByteN()
H A DAMDGPURegisterBankInfo.cpp1482 auto ShiftOffset = Signed ? B.buildAShr(S64, SrcReg, OffsetReg) in applyMappingBFE() local
1484 auto UnmergeSOffset = B.buildUnmerge({S32, S32}, ShiftOffset); in applyMappingBFE()
1519 auto SignBit = B.buildShl(S64, ShiftOffset, ExtShift); in applyMappingBFE()
H A DSIISelLowering.cpp11385 unsigned ShiftOffset = 8 * Offset; in performCvtF32UByteNCombine() local
11387 ShiftOffset -= C->getZExtValue(); in performCvtF32UByteNCombine()
11389 ShiftOffset += C->getZExtValue(); in performCvtF32UByteNCombine()
11391 if (ShiftOffset < 32 && (ShiftOffset % 8) == 0) { in performCvtF32UByteNCombine()
11392 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + ShiftOffset / 8, SL, in performCvtF32UByteNCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp1329 SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, AmtVT); in PromoteIntRes_FunnelShift() local
1330 Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset); in PromoteIntRes_FunnelShift()
1335 Amt = DAG.getNode(ISD::ADD, DL, AmtVT, Amt, ShiftOffset); in PromoteIntRes_FunnelShift()