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Searched refs:ShiftLHS (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp781 MachineInstr *ShiftLHS = in getCmpOperandFoldingProfit() local
787 if (IsSupportedExtend(*ShiftLHS)) in getCmpOperandFoldingProfit()
H A DAArch64InstructionSelector.cpp6546 MachineOperand &ShiftLHS = ShiftInst->getOperand(1); in selectShiftedRegister() local
6547 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp13657 SDValue ShiftLHS = N->getOperand(0); in isDesirableToCommuteWithShift() local
13662 if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) && in isDesirableToCommuteWithShift()
13663 isa<ConstantSDNode>(ShiftLHS.getOperand(1))) { in isDesirableToCommuteWithShift()
13664 uint64_t TruncMask = ShiftLHS.getConstantOperandVal(1); in isDesirableToCommuteWithShift()
13666 ShiftLHS.getOperand(0).getOpcode() == ISD::SRL && in isDesirableToCommuteWithShift()
13667 isa<ConstantSDNode>(ShiftLHS.getOperand(0).getOperand(1))) in isDesirableToCommuteWithShift()
14630 uint32_t ShiftLHS = 0; in tryCombineToEXTR() local
14632 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi)) in tryCombineToEXTR()
14646 if (ShiftLHS + ShiftRHS != VT.getSizeInBits()) in tryCombineToEXTR()
14651 std::swap(ShiftLHS, ShiftRHS); in tryCombineToEXTR()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp30742 unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate() local
30756 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(4, DL, VT)), in LowerRotate()
30766 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(2, DL, VT)), in LowerRotate()
30776 DAG.getNode(ShiftLHS, DL, VT, R, DAG.getConstant(1, DL, VT)), in LowerRotate()