| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 235 SDValue Shamt = Op.getOperand(2); in lowerShiftLeftParts() local
252 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
275 SDValue Shamt = Op.getOperand(2); in lowerShiftRightParts() local
483 uint64_t Shamt; in performSRLCombine() local
496 Shamt = CN->getZExtValue(); in performSRLCombine()
497 if (MaskIdx <= Shamt && Shamt <= MaskIdx + MaskLen - 1) in performSRLCombine()
516 unsigned Shamt; in performORCombine() local
539 (Shamt = CN1->getZExtValue()) == MaskIdx0 && in performORCombine()
558 (Shamt = CN1->getZExtValue()) == MaskIdx0 && in performORCombine()
603 (Shamt = CN1->getZExtValue()) == MaskLen0 && in performORCombine()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsAnalyzeImmediate.cpp | 46 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL() local
47 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
48 AddInstr(SeqLs, Inst(SLL, Shamt)); in GetInstSeqLsSLL()
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| H A D | MipsISelLowering.cpp | 886 unsigned Shamt = CN->getZExtValue(); in performORCombine() local
2585 SDValue Shamt = Op.getOperand(2); in lowerShiftLeftParts() local
2592 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, in lowerShiftLeftParts()
2597 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in lowerShiftLeftParts()
2600 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, in lowerShiftLeftParts()
2614 SDValue Shamt = Op.getOperand(2); in lowerShiftRightParts() local
2630 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, in lowerShiftRightParts()
2638 DL, VT, Hi, Shamt); in lowerShiftRightParts()
2639 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, in lowerShiftRightParts()
4456 unsigned Shamt; in passByValArg() local
[all …]
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| /llvm-project-15.0.7/llvm/test/CodeGen/LoongArch/ |
| H A D | bstrpick_w.ll | 87 ;; Negative test: Shamt < MaskIdx
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| H A D | bstrpick_d.ll | 87 ;; Negative test: Shamt < MaskIdx
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 3256 SDValue Shamt = Op.getOperand(2); in LowerShiftLeftParts() local
3271 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftLeftParts()
3273 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftLeftParts()
3275 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in LowerShiftLeftParts()
3279 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in LowerShiftLeftParts()
3297 SDValue Shamt = Op.getOperand(2); in LowerShiftRightParts() local
3323 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftRightParts()
3325 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftRightParts()
3327 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in LowerShiftRightParts()
3332 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in LowerShiftRightParts()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 4044 SDValue Shamt = Op.getOperand(2); in lowerShiftLeftParts() local
4058 SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); in lowerShiftLeftParts()
4059 SDValue XLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, XLenMinus1); in lowerShiftLeftParts()
4061 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in lowerShiftLeftParts()
4065 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in lowerShiftLeftParts()
4083 SDValue Shamt = Op.getOperand(2); in lowerShiftRightParts() local
4108 SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen); in lowerShiftRightParts()
4109 SDValue XLenMinus1Shamt = DAG.getNode(ISD::XOR, DL, VT, Shamt, XLenMinus1); in lowerShiftRightParts()
4111 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in lowerShiftRightParts()
4116 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in lowerShiftRightParts()
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