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Searched refs:SelectSVERegRegAddrMode (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp340 bool SelectSVERegRegAddrMode(SDValue N, SDValue &Base, SDValue &Offset) { in SelectSVERegRegAddrMode() function in __anon90e2f5bf0111::AArch64DAGToDAGISel
341 return SelectSVERegRegAddrMode(N, Scale, Base, Offset); in SelectSVERegRegAddrMode()
415 bool SelectSVERegRegAddrMode(SDValue N, unsigned Scale, SDValue &Base,
1561 !IsRegImm && SelectSVERegRegAddrMode(OldBase, Scale, NewBase, NewOffset); in findAddrModeSVELoadStore()
5231 bool AArch64DAGToDAGISel::SelectSVERegRegAddrMode(SDValue N, unsigned Scale, in SelectSVERegRegAddrMode() function in AArch64DAGToDAGISel
H A DSVEInstrFormats.td8529 def am_sve_regreg_lsl0 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<0>", []>;
8530 def am_sve_regreg_lsl1 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<1>", []>;
8531 def am_sve_regreg_lsl2 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<2>", []>;
8532 def am_sve_regreg_lsl3 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<3>", []>;
8533 def am_sve_regreg_lsl4 : ComplexPattern<iPTR, 2, "SelectSVERegRegAddrMode<4>", []>;