Searched refs:SelectCC (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1726 SDValue SelectCC = FNeg.getOperand(0); in PerformDAGCombine() local
1727 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1728 SelectCC.getOperand(0).getValueType() != MVT::f32 || // LHS in PerformDAGCombine()
1729 SelectCC.getOperand(2).getValueType() != MVT::f32 || // True in PerformDAGCombine()
1730 !isHWTrueValue(SelectCC.getOperand(2)) || in PerformDAGCombine()
1731 !isHWFalseValue(SelectCC.getOperand(3))) { in PerformDAGCombine()
1736 SelectCC.getOperand(0), // LHS in PerformDAGCombine()
1737 SelectCC.getOperand(1), // RHS in PerformDAGCombine()
1740 SelectCC.getOperand(4)); // CC in PerformDAGCombine()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 226 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3950 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, in SelectCC() function in PPCDAGToDAGISel
4427 SDValue CCReg = SelectCC(LHS, RHS, CC, dl, Chain); in trySETCC()
5565 SelectCC(LHS, RHS, IsUnCmp ? ISD::SETUGT : ISD::SETGT, dl); in Select()
5591 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); in Select()
5779 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6211 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); in lowerFPTRUNC_F64_TO_F16() local
6214 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); in lowerFPTRUNC_F64_TO_F16()
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