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/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/Transforms/
H A Dgl-canonicalize.mlir8 %mid = spv.Select %0, %input, %min : i1, f32
10 %2 = spv.Select %1, %mid, %max : i1, f32
23 %mid = spv.Select %0, %min, %input : i1, f32
25 %2 = spv.Select %1, %max, %mid : i1, f32
40 %2 = spv.Select %1, %mid, %max : i1, f32
55 %2 = spv.Select %1, %max, %mid : i1, f32
70 %2 = spv.Select %1, %mid, %max : i1, si32
85 %2 = spv.Select %1, %max, %mid : i1, si32
130 %2 = spv.Select %1, %mid, %max : i1, i32
145 %2 = spv.Select %1, %max, %mid : i1, i32
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/IR/
H A Dlogical-ops.mlir183 // CHECK : spv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i1
184 %2 = spv.Select %arg0, %0, %1 : i1, i1
191 // CHECK : spv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, i32
192 %2 = spv.Select %arg0, %0, %1 : i1, i32
199 // CHECK : spv.Select {{%.*}}, {{%.*}}, {{%.*}} : i1, f32
200 %2 = spv.Select %arg0, %0, %1 : i1, f32
208 %2 = spv.Select %arg0, %0, %1 : i1, !spv.ptr<f32, Function>
216 %2 = spv.Select %arg0, %0, %1 : i1, vector<3xf32>
224 %2 = spv.Select %arg0, %0, %1 : vector<3xi1>, vector<3xf32>
234 %2 = spv.Select %arg0, %0, %1 : i1
[all …]
/llvm-project-15.0.7/mlir/test/Target/SPIRV/
H A Dlogical-ops.mlir99 // CHECK: spv.Select {{.*}}, {{.*}}, {{.*}} : i1, f32
100 %3 = spv.Select %2, %0, %1 : i1, f32
103 // CHECK: spv.Select {{.*}}, {{.*}}, {{.*}} : i1, vector<4xf32>
104 %6 = spv.Select %2, %4, %5 : i1, vector<4xf32>
106 // CHECK: spv.Select {{.*}}, {{.*}}, {{.*}} : vector<4xi1>, vector<4xf32>
107 %8 = spv.Select %7, %4, %5 : vector<4xi1>, vector<4xf32>
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrMemory.td69 // Select loads with no constant offset.
82 // Select loads with a constant offset.
104 // Select loads with just a constant offset.
145 // Select extending loads with no constant offset.
157 // Select extending loads with a constant offset.
180 // Select extending loads with just a constant offset.
266 // Select stores with no constant offset.
281 // Select stores with a constant offset.
301 // Select stores with just a constant offset.
337 // Select truncating stores with no constant offset.
[all …]
H A DWebAssemblyInstrAtomics.td80 // Select notifys with no constant offset.
90 // Select notifys with a constant offset.
106 // Select notifys with just a constant offset.
129 // Select waits with no constant offset.
148 // Select waits with a constant offset.
171 // Select waits with just a constant offset.
229 // Select loads with no constant offset.
233 // Select loads with a constant offset.
241 // Select loads with just a constant offset.
353 // Select stores with no constant offset.
[all …]
H A DWebAssemblyISelDAGToDAG.cpp65 void Select(SDNode *Node) override;
101 void WebAssemblyDAGToDAGISel::Select(SDNode *Node) { in Select() function in WebAssemblyDAGToDAGISel
/llvm-project-15.0.7/mlir/test/Conversion/MathToSPIRV/
H A Dmath-to-gl-spirv.mlir92 // CHECK: %[[R:.+]] = spv.Select %[[CMP]], %[[SUB2]], %[[SUB1]] : i1, i32
103 // CHECK: spv.Select
118 // CHECK: %[[R:.+]] = spv.Select %[[CMP]], %[[SUB2]], %[[SUB1]] : vector<2xi1>, vector<2xi32>
131 // CHECK: %[[SEL:.+]] = spv.Select %[[LT]], %[[NEG]], %[[POW]] : i1, f32
143 // CHECK: spv.Select
157 // CHECK: %[[SEL:.+]] = spv.Select %[[GE]], %[[ONE]], %[[ZERO]]
173 // CHECK: %[[SEL:.+]] = spv.Select %[[GE]], %[[ONE]], %[[ZERO]]
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A D2009-01-22-SortInvalidation.ll24 …pe, %struct..4sPragmaType, i32, i32, %struct.AggInfo*, i32, i32, %struct.Select*, %struct.Table*, …
46 …Select = type { %struct.ExprList*, i8, i8, i8, i8, i8, i8, i8, %struct.SrcList*, %struct.Expr*, %s…
48 …%struct.SrcList_item = type { i8*, i8*, i8*, %struct.Table*, %struct.Select*, i8, i8, i32, %struct…
49 …%struct.Table = type { i8*, i32, %struct.Column*, i32, %struct.Index*, i32, %struct.Select*, i32, …
53 …%struct.TriggerStep = type { i32, i32, %struct.Trigger*, %struct.Select*, %struct..4sPragmaType, %…
74 …* %pParse, %struct.SrcList* %pTabList, %struct.ExprList* %pList, %struct.Select* %pSelect, %struct…
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A D2009-01-22-SortInvalidation.ll24 …pe, %struct..4sPragmaType, i32, i32, %struct.AggInfo*, i32, i32, %struct.Select*, %struct.Table*, …
46 …Select = type { %struct.ExprList*, i8, i8, i8, i8, i8, i8, i8, %struct.SrcList*, %struct.Expr*, %s…
48 …%struct.SrcList_item = type { i8*, i8*, i8*, %struct.Table*, %struct.Select*, i8, i8, i32, %struct…
49 …%struct.Table = type { i8*, i32, %struct.Column*, i32, %struct.Index*, i32, %struct.Select*, i32, …
53 …%struct.TriggerStep = type { i32, i32, %struct.Trigger*, %struct.Select*, %struct..4sPragmaType, %…
74 …* %pParse, %struct.SrcList* %pTabList, %struct.ExprList* %pList, %struct.Select* %pSelect, %struct…
/llvm-project-15.0.7/mlir/test/Conversion/ArithmeticToSPIRV/
H A Darithmetic-to-spirv.mlir415 // CHECK-COUNT-2: spv.Select
418 // CHECK-COUNT-2: spv.Select
435 // CHECK-COUNT-2: spv.Select
438 // CHECK-COUNT-2: spv.Select
455 // CHECK-COUNT-2: spv.Select
458 // CHECK-COUNT-2: spv.Select
740 // CHECK: spv.Select %{{.*}}, %[[ONE]], %[[ZERO]] : i1, f32
749 // CHECK: spv.Select %{{.*}}, %[[ONE]], %[[ZERO]] : i1, f64
770 %2 = spv.Select %arg0, %1, %0 : vector<4xi1>, vector<4xf64>
806 // CHECK: spv.Select %{{.*}}, %[[ONE]], %[[ZERO]] : i1, i32
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dvplan-widen-select-instruction.ll7 ; * Select condition depending on outer loop iteration variable.
8 ; * Select condidition depending on inner loop iteration variable.
9 ; * Select conditition depending on both outer and inner loop iteration
41 ; Select condition is loop invariant for both inner and outer loop.
88 ; Select condition only depends on outer loop iteration variable.
135 ; Select condition only depends on inner loop iteration variable.
184 ; Select condition depends on both inner and outer loop iteration variables.
/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/X86/
H A Dsink-addrmode-select.ll6 ; Select when both offset and scale reg are present.
23 ; Select when both GV and base reg are present.
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dudiv_select_to_select_shift.ll5 ; udiv X, (Select Cond, C1, C2) --> Select Cond, (shr X, C1), (shr X, C2)
/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Dmisc-ops-to-llvm.mlir42 // spv.Select
48 %0 = spv.Select %arg0, %arg1, %arg1 : i1, vector<3xi32>
50 %1 = spv.Select %arg0, %arg2, %arg2 : i1, f32
57 %0 = spv.Select %arg0, %arg1, %arg1 : vector<2xi1>, vector<2xi32>
/llvm-project-15.0.7/llvm/docs/CommandGuide/
H A Dllvm-otool.rst24 Select slice of universal Mach-O file.
76 Select cpu for disassembly.
/llvm-project-15.0.7/clang/utils/TableGen/
H A DClangDiagnosticsEmitter.cpp729 CASE(Select); in Visit()
927 SelectPiece Select(MT_Diff); in VisitDiff() local
928 Select.Options.push_back(&FirstOption); in VisitDiff()
929 Select.Options.push_back(P->Parts[3]); in VisitDiff()
931 VisitSelect(&Select); in VisitDiff()
1074 Select->Options.push_back( in parseDiagText()
1079 Select->Index = parseModifier(Text); in parseDiagText()
1080 Parsed.push_back(Select); in parseDiagText()
1147 Select->Options.push_back(New<TextPiece>("")); in parseDiagText()
1149 Select->Index = parseModifier(Text); in parseDiagText()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dcpu.ll5 ; CHECK-NEXT: generic - Select the generic processor.
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp33 void Select(SDNode *N) override;
85 void R600DAGToDAGISel::Select(SDNode *N) { in Select() function in R600DAGToDAGISel
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUModifierSyntax.rst1132 dpp8:[{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7},{0..7}] Select lanes to read from.
1782 op_sel:[{0..1}] Select operand bits for instructions with 1 source operand.
1783 op_sel:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
1784 op_sel:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
1815 op_sel_hi:[{0..1}] Select operand bits for instructions with 1 source operand.
1816 op_sel_hi:[{0..1},{0..1}] Select operand bits for instructions with 2 source operands.
1817 op_sel_hi:[{0..1},{0..1},{0..1}] Select operand bits for instructions with 3 source operands.
1891 neg_hi:[{0..1}] Select affected operands for instructions with 1 source operand.
1945 op_sel:[{0..1},{0..1},{0..1}] Select location of each 16-bit source operand.
1977 op_sel_hi:[{0..1},{0..1},{0..1}] Select size of each source operand.
[all …]
/llvm-project-15.0.7/llvm/lib/Transforms/Scalar/
H A DLoopDeletion.cpp202 } else if (auto *Select = dyn_cast<SelectInst>(V)) { in getValueOnFirstIteration() local
204 getValueOnFirstIteration(Select->getCondition(), FirstIterValue, SQ); in getValueOnFirstIteration()
206 auto *Selected = C->isAllOnesValue() ? Select->getTrueValue() in getValueOnFirstIteration()
207 : Select->getFalseValue(); in getValueOnFirstIteration()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelDAGToDAG.cpp44 void Select(SDNode *N) override;
169 void ARCDAGToDAGISel::Select(SDNode *N) { in Select() function in ARCDAGToDAGISel
/llvm-project-15.0.7/lldb/include/lldb/Utility/
H A DSelectHelper.h50 lldb_private::Status Select();
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/
H A Dgcc-examples.ll11 ; Select VF = 8;
47 ; Select VF=4 because sext <8 x i1> to <8 x i32> is expensive.
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.h39 void Select(SDNode *Node) override;
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h164 Select, enumerator
348 bool isSelect() const { return Flags & (1ULL << MCID::Select); } in isSelect()

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