| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64MacroFusion.cpp | 24 if (SecondMI.getOpcode() != AArch64::Bcc) in isArithmeticBccPair()
72 if (SecondMI.getOpcode() != AArch64::CBZW && in isArithmeticCbzPair()
73 SecondMI.getOpcode() != AArch64::CBZX && in isArithmeticCbzPair()
74 SecondMI.getOpcode() != AArch64::CBNZW && in isArithmeticCbzPair()
75 SecondMI.getOpcode() != AArch64::CBNZX) in isArithmeticCbzPair()
123 switch (SecondMI.getOpcode()) { in isAESPair()
164 SecondMI.getOpcode() == AArch64::ADDXri) in isAdrpAddPair()
176 SecondMI.getOperand(3).getImm() == 16)) in isLiteralsPair()
182 SecondMI.getOperand(3).getImm() == 16)) in isLiteralsPair()
199 switch (SecondMI.getOpcode()) { in isAddressLdStPair()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCMacroFusion.cpp | 69 const MachineInstr &SecondMI, in matchingRegOps() argument
104 const MachineOperand &RA = SecondMI.getOperand(1); in checkOpConstraints()
113 const MachineOperand &RT = SecondMI.getOperand(0); in checkOpConstraints()
121 if (!matchingRegOps(SecondMI, 0, SecondMI, 2) || in checkOpConstraints()
142 if (SecondMI.getOpcode() == PPC::LD) in checkOpConstraints()
174 if (SecondMI.getOpcode() == PPC::CMPDI && in checkOpConstraints()
175 matchingImmOps(SecondMI, 2, -1, 16)) in checkOpConstraints()
177 return matchingImmOps(SecondMI, 2, 0) || matchingImmOps(SecondMI, 2, 1); in checkOpConstraints()
186 return matchingImmOps(SecondMI, 2, 0) || matchingImmOps(SecondMI, 2, 1) || in checkOpConstraints()
187 matchingImmOps(SecondMI, 2, -1, 16); in checkOpConstraints()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | GCNCreateVOPD.cpp | 63 auto *SecondMI = Pair.second; in doReplace() local
65 unsigned Opc2 = SecondMI->getOpcode(); in doReplace()
75 .add(SecondMI->getOperand(0)) in doReplace()
91 VOPDInst.add(SecondMI->getOperand(1)); in doReplace()
98 VOPDInst.add(SecondMI->getOperand(2)); in doReplace()
99 VOPDInst.add(SecondMI->getOperand(3)); in doReplace()
107 VOPDInst.copyImplicitOps(*SecondMI); in doReplace()
112 SecondMI->eraseFromParent(); in doReplace()
139 auto *SecondMI = &*MII; in runOnMachineFunction() local
147 Pair = {FirstMI, SecondMI}; in runOnMachineFunction()
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| H A D | GCNVOPDUtils.cpp | 38 const MachineInstr &SecondMI) { in checkVOPDRegConstraints() argument
57 if (&*MII == &SecondMI) in checkVOPDRegConstraints()
63 for (const auto &Use : SecondMI.uses()) in checkVOPDRegConstraints()
72 ComponentInfo CInfo[] = {ComponentInfo(FirstMI), ComponentInfo(SecondMI)}; in checkVOPDRegConstraints()
139 << "\n\tY: " << SecondMI << "\n"); in checkVOPDRegConstraints()
149 const MachineInstr &SecondMI) { in shouldScheduleVOPDAdjacent() argument
151 unsigned Opc2 = SecondMI.getOpcode(); in shouldScheduleVOPDAdjacent()
165 return checkVOPDRegConstraints(STII, *FirstMI, SecondMI); in shouldScheduleVOPDAdjacent()
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| H A D | AMDGPUMacroFusion.cpp | 29 const MachineInstr &SecondMI) { in shouldScheduleAdjacent() argument
32 switch (SecondMI.getOpcode()) { in shouldScheduleAdjacent()
46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent()
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| H A D | GCNVOPDUtils.h | 26 const MachineInstr &SecondMI);
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVMacroFusion.cpp | 26 const MachineInstr &SecondMI) { in isLUIADDI() argument
27 if (SecondMI.getOpcode() != RISCV::ADDI && in isLUIADDI()
28 SecondMI.getOpcode() != RISCV::ADDIW) in isLUIADDI()
39 if (!SecondMI.getOperand(1).isReg()) in isLUIADDI()
45 if (SecondMI.getOperand(1).getReg() != FirstDest) in isLUIADDI()
50 return FirstDest.isVirtual() || SecondMI.getOperand(0).getReg() == FirstDest; in isLUIADDI()
56 const MachineInstr &SecondMI) { in shouldScheduleAdjacent() argument
59 if (ST.hasLUIADDIFusion() && isLUIADDI(FirstMI, SecondMI)) in shouldScheduleAdjacent()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMMacroFusion.cpp | 23 const MachineInstr &SecondMI) { in isAESPair() argument
25 switch(SecondMI.getOpcode()) { in isAESPair()
39 const MachineInstr &SecondMI) { in isLiteralsPair() argument
42 SecondMI.getOpcode() == ARM::MOVTi16) in isLiteralsPair()
54 const MachineInstr &SecondMI) { in shouldScheduleAdjacent() argument
57 if (ST.hasFuseAES() && isAESPair(FirstMI, SecondMI)) in shouldScheduleAdjacent()
59 if (ST.hasFuseLiterals() && isLiteralsPair(FirstMI, SecondMI)) in shouldScheduleAdjacent()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86MacroFusion.cpp | 38 const MachineInstr &SecondMI) { in shouldScheduleAdjacent() argument
45 const X86::SecondMacroFusionInstKind BranchKind = classifySecond(SecondMI); in shouldScheduleAdjacent()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MacroFusion.h | 35 const MachineInstr &SecondMI)>;
|