Home
last modified time | relevance | path

Searched refs:Scheduling (Results 1 – 25 of 143) sorted by relevance

123456

/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfusion-load-store.ll11 ; CHECK: ********** MI Scheduling **********
19 ; CHECK: ********** MI Scheduling **********
40 ; CHECK: ********** MI Scheduling **********
48 ; CHECK: ********** MI Scheduling **********
69 ; CHECK: ********** MI Scheduling **********
77 ; CHECK: ********** MI Scheduling **********
98 ; CHECK: ********** MI Scheduling **********
106 ; CHECK: ********** MI Scheduling **********
127 ; CHECK: ********** MI Scheduling **********
135 ; CHECK: ********** MI Scheduling **********
[all …]
H A Dread-set-flm.ll20 ; LOG: *** MI Scheduling ***
23 ; LOG: *** MI Scheduling ***
27 ; LOG: *** MI Scheduling ***
55 ; LOG: ***** MI Scheduling *****
58 ; LOG: ***** MI Scheduling *****
62 ; LOG: ***** MI Scheduling *****
H A Dmacro-fusion.ll9 ; CHECK-P8: ********** MI Scheduling **********
14 ; CHECK-P8: ********** MI Scheduling **********
H A Dscheduling-mem-dependency.ll7 ; CHECK: ********** MI Scheduling **********
51 ; CHECK-P9: ********** MI Scheduling **********
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcortex-a57-misched-alu.ll7 ; CHECK: ********** MI Scheduling **********
35 ; CHECK: Scheduling
41 ; CHECK: Scheduling
47 ; CHECK: Scheduling
53 ; CHECK: Scheduling
59 ; CHECK: Scheduling
H A Dsingle-issue-r52.mir21 # CHECK: ********** MI Scheduling **********
33 # TOPDOWN: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
35 # TOPDOWN: Scheduling SU(2) %4:dpr = VADDv8i8
37 # BOTTOMUP: Scheduling SU(2) %4:dpr = VADDv8i8
38 # BOTTOMUP: Scheduling SU(1) %1:qqpr = VLD4d8Pseudo
H A Dpostrasched.ll6 ; CHECK: ********** MI Scheduling **********
9 ; CHECK: ********** MI Scheduling **********
22 ; CHECK: ********** List Scheduling **********
H A Dproc-resource-sched.ll17 ; CHECK-R52: MI Scheduling
19 ; CHECK-R52: Scheduling SU(5) %5:gpr = nsw ADDrr %3:gpr, %2:gpr, 14, $noreg, $noreg
20 ; CHECK-R52: Scheduling SU(4) %4:gpr = nsw ADDrr %1:gpr, %0:gpr, 14, $noreg, $noreg
H A Dcortex-a57-misched-vfma.ll7 ; CHECK: ********** MI Scheduling **********
46 ; CHECK: ********** MI Scheduling **********
84 ; CHECK: ********** MI Scheduling **********
123 ; CHECK: ********** MI Scheduling **********
161 ; CHECK: ********** MI Scheduling **********
180 ; CHECK: ********** MI Scheduling **********
H A Dcortex-a57-misched-vstm.ll4 ; CHECK: ********** MI Scheduling **********
6 ; CHECK: ********** MI Scheduling **********
H A Dcortex-a57-misched-ldm.ll4 ; CHECK: ********** MI Scheduling **********
6 ; CHECK: ********** MI Scheduling **********
H A Dcortex-a57-misched-vldm.ll4 ; CHECK: ********** MI Scheduling **********
6 ; CHECK: ********** MI Scheduling **********
H A Dcortex-a57-misched-stm.ll5 ; CHECK: ********** MI Scheduling **********
7 ; CHECK: ********** MI Scheduling **********
H A Dcortex-a57-misched-stm-wrback.ll5 ; CHECK: ********** MI Scheduling **********
7 ; CHECK: ********** MI Scheduling **********
H A Dcortex-a57-misched-ldm-wrback.ll9 ; CHECK: ********** MI Scheduling **********
11 ; CHECK: ********** MI Scheduling **********
H A D2012-06-12-SchedMemLatency.ll7 ; CHECK: ** List Scheduling
17 ; CHECK: ** List Scheduling
H A Dcortex-a57-misched-vldm-wrback.ll9 ; CHECK: ********** MI Scheduling **********
11 ; CHECK: ********** MI Scheduling **********
H A Dcortex-a57-misched-vstm-wrback.ll4 ; CHECK: ********** MI Scheduling **********
6 ; CHECK: ********** MI Scheduling **********
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-ldp-cluster.ll6 ; CHECK: ********** MI Scheduling **********
21 ; CHECK: ********** MI Scheduling **********
37 ; CHECK: ********** MI Scheduling **********
52 ; CHECK: ********** MI Scheduling **********
70 ; CHECK: ********** MI Scheduling **********
88 ; CHECK: ********** MI Scheduling **********
103 ; CHECK: ********** MI Scheduling **********
H A Daarch64-stp-cluster.ll5 ; CHECK: ********** MI Scheduling **********
26 ; CHECK: ********** MI Scheduling **********
47 ; CHECK:********** MI Scheduling **********
68 ; CHECK:********** MI Scheduling **********
89 ; CHECK:********** MI Scheduling **********
110 ; CHECK:********** MI Scheduling **********
131 ; CHECK: ********** MI Scheduling **********
151 ; CHECK: ********** MI Scheduling **********
200 ; CHECK: ********** MI Scheduling **********
220 ; CHECK: ********** MI Scheduling **********
H A Darm64-misched-basic-A53.ll9 ; CHECK: ********** MI Scheduling **********
85 ; CHECK: ********** MI Scheduling **********
131 ; CHECK: ********** MI Scheduling **********
179 ; CHECK: ********** MI Scheduling **********
H A Darm64-misched-forwarding-A53.ll7 ; CHECK: ********** MI Scheduling **********
/llvm-project-15.0.7/polly/lib/CodeGen/
H A DLoopGeneratorsKMP.cpp201 OMPGeneralSchedulingType Scheduling = in createSubFn() local
204 switch (Scheduling) { in createSubFn()
258 if (Scheduling == OMPGeneralSchedulingType::StaticChunked) { in createSubFn()
268 if (Scheduling == OMPGeneralSchedulingType::StaticChunked) { in createSubFn()
307 if (Scheduling == OMPGeneralSchedulingType::StaticChunked || in createSubFn()
308 Scheduling == OMPGeneralSchedulingType::StaticNonChunked) { in createSubFn()
562 int ChunkSize, OMPGeneralSchedulingType Scheduling) const { in getSchedType()
563 if (ChunkSize == 0 && Scheduling == OMPGeneralSchedulingType::StaticChunked) in getSchedType()
566 return Scheduling; in getSchedType()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kSchedule.td1 //===-- M68kSchedule.td - M68k Scheduling Definitions ------*- tablegen -*-===//
14 /// This is a very general M68k Scheduling Model and best suited for the very
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Dopt-codegen-no-target-machine.ll3 ; CHECK: Trying to construct TargetPassConfig without a target machine. Scheduling a CodeGen pass w…

123456