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Searched refs:SchedRead (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td109 def ReadJmp : SchedRead;
110 def ReadJalr : SchedRead;
111 def ReadCSR : SchedRead;
112 def ReadMemBase : SchedRead;
113 def ReadFMemBase : SchedRead;
114 def ReadStoreData : SchedRead;
115 def ReadIALU : SchedRead;
117 def ReadShiftImm : SchedRead;
119 def ReadShiftReg : SchedRead;
121 def ReadIDiv : SchedRead;
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H A DRISCVScheduleB.td96 def ReadRotateImm : SchedRead;
97 def ReadRotateImm32 : SchedRead;
98 def ReadRotateReg : SchedRead;
99 def ReadRotateReg32 : SchedRead;
100 def ReadCLZ : SchedRead;
101 def ReadCLZ32 : SchedRead;
102 def ReadCTZ : SchedRead;
103 def ReadCTZ32 : SchedRead;
104 def ReadCPOP : SchedRead;
105 def ReadCPOP32 : SchedRead;
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H A DRISCVScheduleV.td273 def ReadVLDX : SchedRead;
274 def ReadVSTX : SchedRead;
276 def ReadVSTE8V : SchedRead;
277 def ReadVSTE16V : SchedRead;
278 def ReadVSTE32V : SchedRead;
279 def ReadVSTE64V : SchedRead;
281 def ReadVSTM : SchedRead;
283 def ReadVLDSX : SchedRead;
284 def ReadVSTSX : SchedRead;
285 def ReadVSTS8V : SchedRead;
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td27 def ReadI : SchedRead; // ALU
28 def ReadISReg : SchedRead; // ALU of Shifted-Reg
29 def ReadIEReg : SchedRead; // ALU of Extended-Reg
31 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
35 def ReadID : SchedRead; // 32/64-bit Divide
38 def ReadIM : SchedRead; // 32/64-bit Multiply
39 def ReadIMA : SchedRead; // 32/64-bit Multiply Accumulate
50 def ReadST : SchedRead; // Read the stored value.
51 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
88 def ReadVLD : SchedRead;
H A DAArch64SchedThunderX.td191 // Subtarget-specific SchedRead types.
H A DAArch64SchedA53.td149 // Subtarget-specific SchedRead types.
H A DAArch64SchedA55.td208 // Subtarget-specific SchedRead types.
H A DAArch64SchedCyclone.td865 // Unused SchedRead types
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td13 def P10BR_Read : SchedRead;
14 def P10DF_Read : SchedRead;
15 def P10DV_Read : SchedRead;
16 def P10DX_Read : SchedRead;
17 def P10F2_Read : SchedRead;
18 def P10FX_Read : SchedRead;
19 def P10LD_Read : SchedRead;
20 def P10MU_Read : SchedRead;
21 def P10PM_Read : SchedRead;
22 def P10ST_Read : SchedRead;
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/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSchedule.td213 // listed for implicit def operands. SchedRead types may optionally
219 // single SchedWrite and single SchedRead in any order.
229 class SchedRead : SchedReadWrite;
326 // A processor may define a ReadAdvance associated with a SchedRead
338 SchedRead ReadType = read;
341 // Directly associate a new SchedRead type with a delay and optional
346 // Define SchedRead defaults. Reads seldom need special treatment.
347 def ReadDefault : SchedRead;
415 // A SchedReadVariant is a single SchedRead type that maps to a list
416 // of SchedRead types under the conditions defined by its predicates.
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSchedule.td61 def ReadALU : SchedRead;
67 def ReadALUsr : SchedRead; // Some operands are read later.
79 def ReadMUL : SchedRead;
86 def ReadMAC : SchedRead;
118 def ReadFPMUL : SchedRead; // multiplier read
119 def ReadFPMAC : SchedRead; // accumulator read
H A DARMScheduleR52.td9 // This file defines the SchedRead/Write data for the ARM Cortex-R52 processor.
46 def R52Read_ISS : SchedRead;
47 def R52Read_EX1 : SchedRead;
48 def R52Read_EX2 : SchedRead;
49 def R52Read_WRI : SchedRead;
50 def R52Read_F0 : SchedRead; // F0 maps to ISS stage of integer pipe
51 def R52Read_F1 : SchedRead;
52 def R52Read_F2 : SchedRead;
H A DARMScheduleM4.td9 // This file defines the SchedRead/Write data for the ARM Cortex-M4 processor.
H A DARMScheduleM7.td9 // This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
H A DARMScheduleA57.td775 // def A57ReadVFMA : SchedRead;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86Schedule.td15 def ReadAfterLd : SchedRead;
16 def ReadAfterVecLd : SchedRead;
17 def ReadAfterVecXLd : SchedRead;
18 def ReadAfterVecYLd : SchedRead;
22 // This SchedRead describes a bypass delay caused by data being moved from the
24 def ReadInt2Fpu : SchedRead;
48 // The SchedRead to tag register operands than don't need to be ready
50 SchedRead ReadAfterFold;
54 multiclass X86SchedWritePair<SchedRead ReadAfter = ReadAfterLd> {
H A DX86InstrSSE.td848 SchedRead Int2Fpu = ReadDefault> {
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp110 Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
916 Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead, in FindReadAdvance() argument
919 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) in FindReadAdvance()
920 return SchedRead.TheDef; in FindReadAdvance()
924 for (Record *A : SchedRead.Aliases) { in FindReadAdvance()
947 || SchedRead.TheDef == RA->getValueAsDef("ReadType")) { in FindReadAdvance()
958 if (!ResDef && SchedRead.TheDef->getName() != "ReadDefault") { in FindReadAdvance()
961 SchedRead.TheDef->getName()); in FindReadAdvance()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td35 def RegReadAdv : SchedRead;
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSISchedule.td27 def MIVGPRRead : SchedRead;
28 def MIMFMARead : SchedRead;