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Searched refs:SZ (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Davx512fp16-combine-vfmac-fadd.ll7 ; NO-SZ-LABEL: test1:
10 ; NO-SZ-NEXT: retq
12 ; HAS-SZ-LABEL: test1:
17 ; HAS-SZ-NEXT: retq
28 ; NO-SZ-LABEL: test2:
31 ; NO-SZ-NEXT: retq
33 ; HAS-SZ-LABEL: test2:
38 ; HAS-SZ-NEXT: retq
49 ; NO-SZ-LABEL: test3:
52 ; NO-SZ-NEXT: retq
[all …]
/llvm-project-15.0.7/compiler-rt/test/msan/
H A Dbsearch.cpp32 constexpr size_t SZ = 27; in main() local
33 long p[SZ + 1]; in main()
34 for (int i = 0; i < SZ + 1; ++i) in main()
36 p[SZ] = SZ / 3; in main()
38 __msan_poison(p, sizeof(long) * SZ / 2); in main()
40 __msan_poison(p + SZ, sizeof(long)); in main()
42 const long *r = (const long *)bsearch(p + SZ, p, SZ, sizeof(long), compar); in main()
45 assert(r == p + SZ / 3); in main()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrArithmetic.td198 foreach SZ = [8, 16, 32] in {
234 def NAME#SZ#"pd" : MxBiArOp_MR<MN,
239 def NAME#SZ#"fd" : MxBiArOp_MR<MN,
244 def NAME#SZ#"jd" : MxBiArOp_MR<MN,
249 def NAME#SZ#"pi" : MxBiArOp_MI<MN,
269 } // foreach SZ
271 foreach SZ = [16, 32] in
351 foreach SZ = [8, 16, 32] in
352 def NAME#SZ#"dd" : MxBiArOp_R_RRX<MN, NODE, !cast<MxType>("MxType"#SZ#"d"), CMD>;
370 foreach SZ = [8, 16, 32] in {
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/llvm-project-15.0.7/compiler-rt/test/asan/TestCases/Linux/
H A Dodr-violation.cpp48 #ifndef SZ
49 # define SZ 4 macro
53 namespace foo { char G[SZ]; }
/llvm-project-15.0.7/llvm/test/Transforms/LoopIdiom/
H A Dmemcpy.ll9 ; CHECK-NEXT: [[EXITCOND_NOT1:%.*]] = icmp eq i64 [[SZ:%.*]], 0
12 ; CHECK-NEXT: [[TMP0:%.*]] = shl nuw i64 [[SZ]], 2
23 ; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[SZ]]
61 ; CHECK-NEXT: [[EXITCOND_NOT1:%.*]] = icmp eq i64 [[SZ:%.*]], 0
64 ; CHECK-NEXT: [[TMP0:%.*]] = shl nuw i64 [[SZ]], 2
75 ; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[SZ]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dalloca.ll5 ; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
7 ; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dframe-index-elimination.ll199 ; GFX9-FLATSCR-DAG: s_add_i32 [[SZ:[^,]+]], s32, 0x200
200 ; GFX9-FLATSCR: v_mov_b32_e32 [[VZ:v[0-9]+]], [[SZ]]
225 ; GFX9-FLATSCR-DAG: s_add_i32 [[SZ:[^,]+]], s32, 0x200
226 ; GFX9-FLATSCR: v_mov_b32_e32 [[VZ:v[0-9]+]], [[SZ]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbuiltin-dynamic-object-size.ll150 ; CHECK: [[TMP:%.*]] = icmp ne i64 [[SZ:%.*]], -1
153 ; CHECK: call void @fortified_chk(i8* %obj, i64 [[SZ]])
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3623 unsigned SZ = ValueTy->getPrimitiveSizeInBits(); in emitLoadLinked() local
3624 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported"); in emitLoadLinked()
3625 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked in emitLoadLinked()
3631 Builder.getIntNTy(SZ)->getPointerTo(PtrTy->getAddressSpace()); in emitLoadLinked()
3647 unsigned SZ = Ty->getPrimitiveSizeInBits(); in emitStoreConditional() local
3649 Type *CastTy = Builder.getIntNTy(SZ); in emitStoreConditional()
3650 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported"); in emitStoreConditional()
3651 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked in emitStoreConditional()
/llvm-project-15.0.7/llvm/test/Transforms/SCCP/
H A Dconditions-ranges.ll174 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 4088, [[SZ:%.*]]
177 ; CHECK-NEXT: [[DIV:%.*]] = udiv i64 4088, [[SZ]]
755 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 4088, [[SZ:%.*]]
758 ; CHECK-NEXT: [[DIV:%.*]] = udiv i64 4088, [[SZ]]
783 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[SZ:%.*]], 4088
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dcanonicalize.mlir1252 // CHECK-SAME: %[[IV:.*]]: index, %[[SZ:.*]]: index)
1261 // CHECK-SAME: [%[[IV]], 16] [%[[SZ]], 8]
1267 // CHECK-SAME: [%[[IV]], 16] [%[[SZ]], 8]
1283 // CHECK-SAME: %[[IV:.*]]: index, %[[SZ:.*]]: index)
/llvm-project-15.0.7/llvm/lib/Analysis/
H A DScalarEvolution.cpp1233 if (const SCEVZeroExtendExpr *SZ = dyn_cast<SCEVZeroExtendExpr>(Op)) in getTruncateExpr() local
1234 return getTruncateOrZeroExtend(SZ->getOperand(), Ty, Depth + 1); in getTruncateExpr()
1608 if (const SCEVZeroExtendExpr *SZ = dyn_cast<SCEVZeroExtendExpr>(Op)) in getZeroExtendExpr() local
1609 return getZeroExtendExpr(SZ->getOperand(), Ty, Depth + 1); in getZeroExtendExpr()
1914 if (const SCEVZeroExtendExpr *SZ = dyn_cast<SCEVZeroExtendExpr>(Op)) in getSignExtendExpr() local
1915 return getZeroExtendExpr(SZ->getOperand(), Ty, Depth + 1); in getSignExtendExpr()
9510 const SCEVZeroExtendExpr *SZ = cast<SCEVZeroExtendExpr>(V); in BuildConstantFromSCEV() local
9511 if (Constant *CastOp = BuildConstantFromSCEV(SZ->getOperand())) in BuildConstantFromSCEV()
9512 return ConstantExpr::getZExt(CastOp, SZ->getType()); in BuildConstantFromSCEV()
/llvm-project-15.0.7/mlir/test/Dialect/LLVMIR/
H A Droundtrip.mlir173 // CHECK: %[[SZ:.*]] = llvm.mlir.constant
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td11160 // CAS SZ |001000|1 |A |1 |Rs |R |11111 |Rn |Rt
11161 // CASP 0|SZ|001000|0 |A |1 |Rs |R |11111 |Rn |Rt
11162 // SWP SZ |111000|A |R |1 |Rs |1 |OPC|00|Rn |Rt
11163 // LD SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |Rt
11164 // ST SZ |111000|A |R |1 |Rs |0 |OPC|00|Rn |11111