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Searched refs:SY (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dmatching-binops.ll20 ; CHECK-NEXT: [[R:%.*]] = and i8 [[A]], [[SY]]
35 ; CHECK-NEXT: [[R:%.*]] = or i8 [[A]], [[SY]]
50 ; CHECK-NEXT: [[R:%.*]] = xor i8 [[A]], [[SY]]
65 ; CHECK-NEXT: [[R:%.*]] = and i8 [[A]], [[SY]]
80 ; CHECK-NEXT: [[R:%.*]] = or i8 [[A]], [[SY]]
95 ; CHECK-NEXT: [[R:%.*]] = xor i8 [[A]], [[SY]]
110 ; CHECK-NEXT: [[R:%.*]] = and i8 [[A]], [[SY]]
125 ; CHECK-NEXT: [[R:%.*]] = or i8 [[A]], [[SY]]
159 ; CHECK-NEXT: [[R:%.*]] = and i8 [[A]], [[SY]]
176 ; CHECK-NEXT: [[R:%.*]] = or i8 [[A]], [[SY]]
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h74 SY = 15 enumerator
80 case SY: return "sy"; in MemBOptToString()
131 SY = 15 enumerator
153 case SY: return "sy"; in InstSyncBOptToString()
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-sub-01.ll38 ; Check the next word up, which should use SY instead of S.
49 ; Check the high end of the aligned SY range.
73 ; Check the high end of the negative aligned SY range.
84 ; Check the low end of the SY range.
121 ; Check that SY allows an index.
H A Dint-ssub-01.ll100 ; Check the next word up, which should use SY instead of S.
118 ; Check the high end of the aligned SY range.
156 ; Check the high end of the negative aligned SY range.
174 ; Check the low end of the SY range.
232 ; Check that SY allows an index.
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.cvt.pk.i16.ll7 ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
8 ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
H A Dllvm.amdgcn.cvt.pk.u16.ll7 ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
8 ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
H A Dllvm.amdgcn.cvt.pknorm.i16.ll7 ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
8 ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
H A Dllvm.amdgcn.cvt.pknorm.u16.ll7 ; GCN-DAG: s_load_dwordx2 s[[[SX:[0-9]+]]:[[SY:[0-9]+]]], s[0:1], 0x{{b|2c}}
8 ; GCN: v_mov_b32_e32 [[VY:v[0-9]+]], s[[SY]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A D2004-11-27-SetCCForCastLargerAndConstant.ll421 ; CHECK-NEXT: [[SY:%.*]] = sext i4 [[Y:%.*]] to i25
422 ; CHECK-NEXT: call void @use(i25 [[SY]])
455 ; CHECK-NEXT: [[SY:%.*]] = sext i4 [[Y:%.*]] to i25
456 ; CHECK-NEXT: call void @use(i25 [[SY]])
457 ; CHECK-NEXT: [[R:%.*]] = icmp ule i25 [[SX]], [[SY]]
H A Dmul-inseltpoison.ll205 ; CHECK-NEXT: [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
206 ; CHECK-NEXT: call void @use32(i32 [[SY]])
220 ; CHECK-NEXT: [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
221 ; CHECK-NEXT: call void @use32(i32 [[SY]])
237 ; CHECK-NEXT: [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
238 ; CHECK-NEXT: call void @use32(i32 [[SY]])
239 ; CHECK-NEXT: [[R:%.*]] = mul nsw i32 [[SY]], [[SX]]
279 ; CHECK-NEXT: [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
280 ; CHECK-NEXT: call void @use32(i32 [[SY]])
H A Dand-xor-or.ll361 ; CHECK-NEXT: [[R:%.*]] = and i8 [[SY]], [[A]]
377 ; CHECK-NEXT: [[R:%.*]] = or i8 [[A]], [[SY]]
394 ; CHECK-NEXT: [[R:%.*]] = xor i8 [[A]], [[SY]]
412 ; CHECK-NEXT: [[R:%.*]] = and i8 [[SY]], [[A]]
429 ; CHECK-NEXT: [[R:%.*]] = or i8 [[SY]], [[A]]
445 ; CHECK-NEXT: [[R:%.*]] = xor i8 [[A]], [[SY]]
480 ; CHECK-NEXT: [[R:%.*]] = or i8 [[SY]], [[A]]
533 ; CHECK-NEXT: [[R:%.*]] = or i8 [[A]], [[SY]]
551 ; CHECK-NEXT: [[R:%.*]] = or i8 [[SY]], [[A]]
4179 ; CHECK-NEXT: call void @use(i32 [[SY]])
[all …]
H A Dmul.ll240 ; CHECK-NEXT: [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
241 ; CHECK-NEXT: call void @use32(i32 [[SY]])
255 ; CHECK-NEXT: [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
256 ; CHECK-NEXT: call void @use32(i32 [[SY]])
272 ; CHECK-NEXT: [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
273 ; CHECK-NEXT: call void @use32(i32 [[SY]])
274 ; CHECK-NEXT: [[R:%.*]] = mul nsw i32 [[SY]], [[SX]]
384 ; CHECK-NEXT: [[SY:%.*]] = sext i1 [[Y:%.*]] to i32
385 ; CHECK-NEXT: call void @use32(i32 [[SY]])
H A Dminmax-intrinsics.ll71 ; CHECK-NEXT: [[SY:%.*]] = sext i5 [[Y:%.*]] to i8
72 ; CHECK-NEXT: call void @use(i8 [[SY]])
2394 ; CHECK-NEXT: [[SY:%.*]] = shufflevector <2 x i8> [[Y:%.*]], <2 x i8> poison, <3 x i32> <i32 1, …
2395 ; CHECK-NEXT: call void @use_vec(<3 x i8> [[SY]])
2437 ; CHECK-NEXT: [[SY:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> poison, <3 x i32> <i32 1, …
2438 ; CHECK-NEXT: [[R:%.*]] = call <3 x i8> @llvm.smax.v3i8(<3 x i8> [[SX]], <3 x i8> [[SY]])
2452 ; CHECK-NEXT: [[SY:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> [[Z]], <3 x i32> <i32 1, i…
2453 ; CHECK-NEXT: [[R:%.*]] = call <3 x i8> @llvm.smax.v3i8(<3 x i8> [[SX]], <3 x i8> [[SY]])
2468 ; CHECK-NEXT: [[SY:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> poison, <3 x i32> <i32 1, …
2469 ; CHECK-NEXT: call void @use_vec(<3 x i8> [[SY]])
[all …]
H A Dsub.ll1765 ; CHECK-NEXT: [[SY:%.*]] = sext <2 x i8> [[Y:%.*]] to <2 x i16>
1766 ; CHECK-NEXT: [[S:%.*]] = sub nuw nsw <2 x i16> [[ZX]], [[SY]]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp961 SDValue SY = (S0.getNode() == I) ? S1 : S0; in isMemOPCandidate() local
971 SDNode *SYNode = SY.getNode(); in isMemOPCandidate()
1011 SDValue SY = SOp.getOperand(2); in ppSimplifyOrSelect0() local
1013 if (IsZero(SY)) { in ppSimplifyOrSelect0()
1018 SDValue NewOr = DAG.getNode(ISD::OR, DLS, VT, SY, VOp); in ppSimplifyOrSelect0()
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp4965 .Case("sy", ARM_MB::SY) in parseMemBarrierOptOperand()
5055 Opt = ARM_ISB::SY; in parseInstSyncBarrierOptOperand()
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dbasic-arm-instructions.s953 dsb SY
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4221 Domain = ARM_MB::SY; in LowerATOMIC_FENCE()
20962 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain; in makeDMB()