| /llvm-project-15.0.7/compiler-rt/lib/builtins/hexagon/ |
| H A D | fastmath2_dlib_asm.S | 78 expa = SXTH(manta)
79 expb = SXTH(mantb)
81 expd = SXTH(expd)
179 expa = SXTH(manta)
180 expb = SXTH(mantb)
182 expd = SXTH(expd)
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| H A D | fastmath_dlib_asm.S | 86 expa = SXTH(manta)
87 expb = SXTH(mantb)
89 expd = SXTH(expd)
221 expa = SXTH(manta)
222 expb = SXTH(mantb)
224 expd = SXTH(expd)
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 47 SXTH, enumerator
66 case AArch64_AM::SXTH: return "sxth"; in getShiftExtendName()
133 case 5: return AArch64_AM::SXTH; in getExtendType()
160 case AArch64_AM::SXTH: return 5; break; in getExtendEncoding()
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | bitfield-extract.ll | 84 ; SHR with multiple uses is fine as SXTH and SBFX are both aliases of SBFM.
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| H A D | sve-intrinsics-conversion.ll | 43 ; SXTH
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| H A D | sve-unary-movprfx.ll | 956 ; SXTH (sve_int_un_pred_arit_0_w)
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | thumb1.txt | 503 # SXTB/SXTH
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| H A D | thumb2.txt | 2193 # SXTH
2247 # SXTH
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| H A D | basic-arm-instructions.txt | 2121 # SXTH
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 23 def CheckExtSXTH : CheckImmOperand_s<3, "AArch64_AM::SXTH">;
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| H A D | AArch64FastISel.cpp | 1154 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
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| H A D | AArch64ISelDAGToDAG.cpp | 643 return AArch64_AM::SXTH; in getExtendTypeForNode()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 563 SXTH, enumerator
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | basic-thumb-instructions.s | 638 @ SXTB/SXTH
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| H A D | basic-thumb2-instructions.s | 3452 @ SXTH
3508 @ SXTH
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| H A D | basic-arm-instructions.s | 3135 @ SXTH
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 300 STORE_OPCODE(SEXT16, SXTH); in OpcodeCache()
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| H A D | ARMFastISel.cpp | 2662 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2902 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 },
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| H A D | ARMScheduleR52.td | 215 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| H A D | ARMScheduleSwift.td | 161 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| H A D | ARMScheduleA57.td | 361 // Sign/zero extend, normal: SXTB, SXTH, UXTB, UXTH
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| H A D | ARMInstrInfo.td | 3721 def SXTH : AI_ext_rrot<0b01101011,
6128 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
6250 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| /llvm-project-15.0.7/bolt/lib/Target/AArch64/ |
| H A D | AArch64MCPlusBuilder.cpp | 555 else if (ExtendType == AArch64_AM::SXTH) in analyzeIndirectBranchFragment()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1380 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
1393 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend64()
3208 .Case("sxth", AArch64_AM::SXTH) in tryParseOptionalShiftExtend()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 6029 case AArch64_AM::SXTH: in isSignExtendShiftType()
6573 return IsLoadStore ? AArch64_AM::InvalidShiftExtend : AArch64_AM::SXTH; in getExtendTypeForInst()
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