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Searched refs:SWL (Results 1 – 11 of 11) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dunaligned-memops.ll17 ; MIPS: SWL [[LWR]], [[COPY]], 0 :: (store (s32) into %ir.b, align 1)
H A Dunaligned-memops-mapping.mir62 SWL %4, %1, 0 :: (store (s32) into %ir.b, align 1)
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dstore_4_unaligned.mir44 ; MIPS32: SWL [[COPY1]], [[ADDiu]], 3 :: (store (s32) into @float_align1, align 1)
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp240 case Mips::SWL: in isBasePlusOffsetMemoryAccess()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.h250 SWL, enumerator
H A DMipsISelLowering.cpp215 case MipsISD::SWL: return "MipsISD::SWL"; in getTargetNodeName()
2772 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, in lowerUnalignedIntStore() local
2774 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); in lowerUnalignedIntStore()
4934 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) in emitSTR_W()
5018 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) in emitSTR_D()
5026 BuildMI(*BB, I, DL, TII->get(Mips::SWL)) in emitSTR_D()
H A DMipsInstructionSelector.cpp471 if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO)) in select()
H A DMipsScheduleP5600.td144 SBE, SHE, SWE, SCE, SWL, SWR, SWLE, SWRE)>;
H A DMipsScheduleGeneric.td576 def : InstRW<[GenericWriteStore], (instrs SWL, SWR)>;
H A DMipsInstrInfo.td142 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
2130 def SWL : MMRel, StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp4519 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; in expandUxw()