| /llvm-project-15.0.7/compiler-rt/lib/xray/ |
| H A D | xray_trampoline_AArch64.S | 22 STP X1, X2, [SP, #-16]!
23 STP X3, X4, [SP, #-16]!
24 STP X5, X6, [SP, #-16]!
25 STP X7, X30, [SP, #-16]!
26 STP Q0, Q1, [SP, #-32]!
27 STP Q2, Q3, [SP, #-32]!
28 STP Q4, Q5, [SP, #-32]!
29 STP Q6, Q7, [SP, #-32]!
32 STP X8, X0, [SP, #-16]!
75 STP X1, X2, [SP, #-16]!
[all …]
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | wineh-frame-predecrement.mir | 4 # Check that the callee-saved registers are saved starting with a STP
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| H A D | intrinsics-memory-barrier.ll | 19 ; Failure to do so, two STRs will collapse into one STP.
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| H A D | arm64-big-endian-varargs.ll | 3 ; Vararg saving must save Q registers using the equivalent of STR/STP.
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| H A D | misched-stp.ll | 6 ; merged into STP.
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| H A D | stp-opt-with-renaming-undef-assert.mir | 13 # This test also checks that pairwise store STP is generated.
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| H A D | aarch64-ldst-modified-baseReg.mir | 34 # CHECK-NOT: STP
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| H A D | ldst-zero.ll | 3 ; Tests to check that zero stores which are generated as STP xzr, xzr aren't
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| H A D | stp-opt-with-renaming.mir | 4 # NO-RENAME-NOT: STP
6 # NO-RENAME: STP
7 # NO-RENAME-NOT: STP
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| H A D | ldst-nopreidx-sp-redzone.mir | 73 # Check that we don't try to combine the SUB with the STP using pre-index addressing
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedFalkorDetails.td | 980 (instregex "^STP(D|S)(i)$")>;
982 (instregex "^STP(D|S)(post|pre)$")>;
1278 (instregex "^STP(W|X)i$")>;
1280 (instregex "^STP(W|X)(post|pre)$")>;
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| H A D | AArch64SchedTSV110.td | 448 def : InstRW<[TSV110Wr_1cyc_1LdSt, WriteAdr], (instregex "^STP(W|X)(post|pre)$")>;
518 def : InstRW<[TSV110Wr_2cyc_2LdSt, WriteAdr], (instregex "^STP[SDQ](post|pre)")>;
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| H A D | AArch64SchedKryoDetails.td | 2074 (instregex "STP(D|S)i")>;
2080 (instregex "STP(D|S)(post|pre)")>;
2098 (instregex "STP(W|X)i")>;
2104 (instregex "STP(W|X)(post|pre)")>;
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| H A D | AArch64ISelLowering.h | 453 STP, enumerator
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| H A D | AArch64SchedCyclone.td | 276 // STP is a vector op and store, except for QQ, which is just two stores.
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| H A D | AArch64SchedExynosM3.td | 603 WriteAdr], (instregex "^STP[DS](post|pre)")>;
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| H A D | AArch64SchedAmpere1.td | 997 (instregex "STP(W|X)(pre|post)")>;
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| H A D | AArch64SchedExynosM4.td | 725 WriteAdr], (instregex "^STP[SD](post|pre)")>;
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| H A D | AArch64SchedExynosM5.td | 773 WriteAdr], (instregex "^STP[SD](post|pre)")>;
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| H A D | AArch64SchedNeoverseN2.td | 918 (instregex "^STP[SD](pre|post)$")>;
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| H A D | AArch64ISelLowering.cpp | 2312 MAKE_CASE(AArch64ISD::STP) in getTargetNodeName()
5259 AArch64ISD::STP, DL, DAG.getVTList(MVT::Other), in LowerStore128()
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| H A D | AArch64InstrInfo.td | 731 def AArch64stp : SDNode<"AArch64ISD::STP", SDT_AArch64stp, [SDNPHasChain, SDNPMayStore, SDNPMemOper…
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 1412 (instregex "HASH(ST|STP|CHK|CHKP)(8)?$"),
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGStmtOpenMP.cpp | 7604 auto *STP = std::next(I, Stride); in EmitOMPTaskLoopBasedDirective() local
7610 mapParam(CGF, cast<DeclRefExpr>(S.getStrideVariable()), *STP, LoopScope); in EmitOMPTaskLoopBasedDirective()
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