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/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dframe-26.mir13 # CHECK: STG renamable $r6d
78 STG killed renamable $r6d, undef renamable $r1d, 0, $noreg :: (store (s64) into `i32** undef`)
81 STG renamable $r0d, undef renamable $r1d, 0, $noreg :: (store (s64) into `i32** undef`)
97 STG renamable $r4d, undef renamable $r1d, 0, $noreg :: (store (s64) into `i64*** undef`)
103 STG renamable $r10d, undef renamable $r1d, 0, $noreg :: (store (s64) into `i64*** undef`)
108 STG killed renamable $r9d, $noreg, 0, $noreg :: (store (s64) into `i64*** null`)
121 STG killed renamable $r0d, undef renamable $r1d, 0, $noreg :: (store (s64) into `i32** undef`)
167 STG renamable $r0d, undef renamable $r1d, 0, $noreg :: (store (s64) into `i32** undef`)
172 STG renamable $r4d, undef renamable $r1d, 0, $noreg :: (store (s64) into `i64*** undef`)
178 STG renamable $r10d, undef renamable $r1d, 0, $noreg :: (store (s64) into `i64*** undef`)
[all …]
H A Dint-move-07.ll5 ; Check STG with no displacement.
14 ; Check the high end of the aligned STG range.
36 ; Check the high end of the negative aligned STG range.
46 ; Check the low end of the STG range.
68 ; Check that STG allows an index.
H A Dsubregliveness-06.mir188 STG killed %34, killed %35, 0, $noreg :: (store (s64) into %ir.tmp22)
208 STG %10, undef %42:addr64bit, 0, $noreg :: (store (s64) into `i32** undef`)
210 STG %10, $noreg, 0, $noreg :: (store (s64) into `i32** null`)
220 STG %14, undef %43:addr64bit, 0, $noreg :: (store (s64) into `i32** undef`)
228 STG killed %45, killed %46, 0, $noreg :: (store (s64) into %ir.tmp38)
H A Dint-const-06.ll69 ; Check the next doubleword up, which is out of range. We prefer STG
81 ; Check negative displacements, for which we again prefer STG.
H A Dfoldmemop-vec-cmp.mir53 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
89 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
127 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
163 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
199 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
237 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
273 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
309 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
347 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
383 STG %4, %2, 0, $noreg :: (store (s64) into %ir.Dst)
[all …]
H A Dcond-store-04.ll37 ; Check the high end of the aligned STG range.
71 ; Check the low end of the STG range.
105 ; Check that STG allows an index.
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td68 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, R8, SpLim
72 // Pass in STG registers: F1, ..., F6
75 // Pass in STG registers: D1, ..., D6
78 // Pass in STG registers: XMM1, ..., XMM6
H A DSystemZFrameLowering.cpp640 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG)) in emitPrologue()
835 BuildMI(*MBB, MBBI, DL, ZII->get(SystemZ::STG)) in inlineStackProbe()
1244 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG)) in emitPrologue()
H A DSystemZInstrInfo.cpp1129 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD; in foldMemoryOperandImpl()
1350 splitMove(MI, SystemZ::STG); in expandPostRAPseudo()
1606 StoreOpcode = SystemZ::STG; in getLoadStoreOpcodes()
H A DSystemZScheduleZ196.td192 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZEC12.td200 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZ13.td220 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZ16.td222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZ15.td222 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZScheduleZ14.td221 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "STG(RL)?$")>;
H A DSystemZISelLowering.cpp8801 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false); in EmitInstrWithCustomInserter()
8803 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true); in EmitInstrWithCustomInserter()
H A DSystemZInstrInfo.td504 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsettag-merge.mir30 # A sequence of STG with a register copy in the middle.
H A Dldst-opt-mte.mir5 ### STG and its offset limits
H A Dldst-opt-mte-with-dbg.mir8 ### STG and its offset limits
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td317 // which defines the registers for the Spineless Tagless G-Machine (STG) that
318 // GHC uses to implement lazy evaluation. The generic STG machine has a set of
322 // The STG Machine is documented here:
344 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
H A DAArch64SelectionDAGInfo.cpp137 const unsigned OpCode1 = ZeroData ? AArch64ISD::STZG : AArch64ISD::STG; in EmitUnrolledSetTag()
H A DAArch64ISelLowering.h447 STG, enumerator
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallingConv.td708 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
712 // Pass in STG registers: F1, F2, F3, F4, D1, D2
1020 // Pass in STG registers: Base, Sp, Hp, R1
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMCallingConv.td121 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim

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