Home
last modified time | relevance | path

Searched refs:SRL_VL (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h227 SRL_VL, enumerator
H A DRISCVISelLowering.cpp3632 return lowerVPOp(Op, DAG, RISCVISD::SRL_VL); in LowerOperation()
6063 case ISD::SRL: Opc = RISCVISD::SRL_VL; break; in lowerFixedLengthVectorShiftToRVV()
7259 SDValue LShr32 = DAG.getNode(RISCVISD::SRL_VL, DL, ContainerVT, Vec, in ReplaceNodeResults()
7368 DAG.getNode(RISCVISD::SRL_VL, DL, VecVT, Vec, ThirtyTwoV, Mask, VL); in ReplaceNodeResults()
9203 case RISCVISD::SRL_VL: in PerformDAGCombine()
11694 NODE_NAME_CASE(SRL_VL) in getTargetNodeName()
H A DRISCVInstrInfoVVLPatterns.td78 def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>;