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Searched refs:SOP2 (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dverify-sop.mir3 # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
6 # CHECK: *** Bad machine code: SOP2/SOPC instruction requires too many immediate constants
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td22 field bit SOP2 = 0;
158 let TSFlags{3} = SOP2;
H A DSOPInstructions.td403 // SOP2 Instructions
414 let SOP2 = 1;
433 let SOP2 = 1;
1425 // SOP2 Patterns
1680 // SOP2 - GFX11.
1739 // SOP2 - GFX10.
1762 // SOP2 - GFX6, GFX7.
2340 // SOP2 - GFX9.
H A DSIDefines.h34 SOP2 = 1 << 3, enumerator
H A DSIInstrInfo.h384 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
388 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4128 if (!(Desc.TSFlags & (SIInstrFlags::SOP2 | SIInstrFlags::SOPC))) in validateSOPLiteral()
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX7.rst499 SOP2 section in Instructions
H A DAMDGPUAsmGFX8.rst520 SOP2 section in Instructions
H A DAMDGPUAsmGFX90a.rst595 SOP2 section in Instructions
H A DAMDGPUAsmGFX9.rst683 SOP2 section in Instructions
H A DAMDGPUAsmGFX10.rst1170 SOP2 section in Instructions
H A DAMDGPUAsmGFX1030.rst1080 SOP2 section in Instructions
H A DAMDGPUAsmGFX940.rst577 SOP2 section in Instructions
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUUsage.rst14428 SOP2 subsubsection
14443 For full list of supported instructions, refer to "SOP2 Instructions" in ISA