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Searched refs:SOP (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitterRegSequence.td28 def SOP : RegisterOperand<SRegs>;
31 def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
41 …SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } …
62 def : Pat<(i32 (sext SOP:$src)),
63 (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,
64 (SUBSOME_INSN SOP:$src), sub1)>;
79 def : Pat<(i32 (zext SOP:$src)),
80 (SOME_INSN (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0,
81 (SUBSOME_INSN SOP:$src), sub1))>;
H A DGlobalISelEmitterSubreg.td33 def SOP : RegisterOperand<SRegs>;
36 def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>;
37 def SUBSOME_INSN2 : I<(outs SRegs:$dst), (ins SOP:$src), []>;
53 def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src, sub0)>;
72 def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src, sub0))…
97 def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (COPY_TO_REGCLASS SOP:$src, ERegs)), SOP:$sr…
98 …SERT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SOP:{ *:[i16] }:$src, ERegs:{ *:[i32] }), SO…
106 def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME_INSN SOP:$src), su…
200 def : Pat<(i32 (zext SOP:$src)),
201 (SUBREG_TO_REG (i64 0), (SUBSOME_INSN SOP:$src), sub0)>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td66 // Format< OP[6] | RZ[5] | SOP[3] | OFFSET[18] >
91 // Format< OP[6] | SOP[5] | RZ[5] | IMM[16] >
107 // Format< OP[6] | SOP[5] | RZ[5] | OFFSET[16] >
119 // Format< OP[6] | SOP[5] | 00000[5] | OFFSET[16] >
129 // Format< OP[6] | SOP[5] | RX[5] | 0000000000000000[16] >
155 // Format< OP[6] | SOP[5] | PCODE[5] | 0000000000000000[16] >
168 // Format< OP[6] | SOP[5] | RX[5] | IMM16[16] >
181 // Format< OP[6] | SOP[5] | RX[5] | OFFSET[16] >
195 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | IMM[12] >
236 // Format< OP[6] | RZ[5] | RX[5] | SOP[4] | OFFSET[12] >
[all …]
/llvm-project-15.0.7/llvm/lib/Support/
H A Dregex2.h75 #define SOP(op, opnd) ((op)|(opnd)) macro
H A Dregcomp.c1492 p->strip[p->slen++] = SOP(op, opnd); in doemit()
H A Dregengine.inc632 while (m->g->strip[ss] != SOP(O_BACK, i))
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSOPInstructions.td1 //===-- SOPInstructions.td - SOP Instruction Definitions ------------------===//