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Searched refs:SMLAL (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dmul-v4.s1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
H A Dbasic-arm-instructions.s2427 @ SMLAL
H A Dbasic-thumb2-instructions.s2536 @ SMLAL
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h266 SMLAL, // 64bit Signed Accumulate Multiply enumerator
H A DARMInstrInfo.td4396 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4428 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4581 // Halfword multiply accumulate long: SMLAL<x><y>.
4582 class SMLAL<bits<2> opc1, string asm>
4591 def SMLALBB : SMLAL<0b00, "smlalbb">;
4592 def SMLALBT : SMLAL<0b10, "smlalbt">;
4593 def SMLALTB : SMLAL<0b01, "smlaltb">;
4594 def SMLALTT : SMLAL<0b11, "smlaltt">;
6394 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6405 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
H A DREADME.txt424 Should compile to use SMLAL (Signed Multiply Accumulate Long) which multiplies
H A DARMScheduleR52.td279 "SMLAL", "UMLAL", "SMLALBT",
H A DARMScheduleSwift.td307 (instregex "SMLAL", "UMLAL", "SMLALBT",
H A DARMISelDAGToDAG.cpp3935 case ARMISD::SMLAL:{ in Select()
3949 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
H A DARMScheduleA9.td2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
H A DARMISelLowering.cpp1809 MAKE_CASE(ARMISD::SMLAL) in getTargetNodeName()
12650 SDValue SMLAL = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), in AddCombineTo64BitSMLAL16() local
12653 SDValue HiMLALResult(SMLAL.getNode(), 1); in AddCombineTo64BitSMLAL16()
12654 SDValue LoMLALResult(SMLAL.getNode(), 0); in AddCombineTo64BitSMLAL16()
12743 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
12793 FinalOpc == ARMISD::SMLAL && !AddeSubeNode->hasAnyUseOfValue(1) && in AddCombineTo64bitMLAL()
H A DARMInstrFormats.td1011 // SMLAL*
H A DARMInstrThumb2.td3147 // Halfword multiple accumulate long: SMLAL<x><y>
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td529 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
H A DAArch64InstrInfo.td5230 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
6499 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dbasic-arm-instructions.txt1605 # SMLAL
H A Dthumb2.txt1785 # SMLAL
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-advsimd.s1171 ; AdvSIMD SMLAL
/llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8304 case ARM::SMLAL: in validateInstruction()