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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/longbranch/
H A Dbranch-limits-int.mir115 ; MIPS: $zero = SLL $zero, 0
120 ; MIPS: $zero = SLL $zero, 0
127 ; MIPS: $zero = SLL $zero, 0
134 ; PIC: $zero = SLL $zero, 0
156 ; PIC: $zero = SLL $zero, 0
214 ; MIPS: $zero = SLL $zero, 0
219 ; MIPS: $zero = SLL $zero, 0
233 ; PIC: $zero = SLL $zero, 0
255 ; PIC: $zero = SLL $zero, 0
332 ; PIC: $zero = SLL $zero, 0
[all …]
H A Dbranch-limits-int-mips64.mir120 ; MIPS64: $zero = SLL $zero, 0
125 ; MIPS64: $zero = SLL $zero, 0
140 ; PIC: $zero = SLL $zero, 0
222 ; MIPS64: $zero = SLL $zero, 0
227 ; MIPS64: $zero = SLL $zero, 0
242 ; PIC: $zero = SLL $zero, 0
324 ; MIPS64: $zero = SLL $zero, 0
344 ; PIC: $zero = SLL $zero, 0
446 ; PIC: $zero = SLL $zero, 0
548 ; PIC: $zero = SLL $zero, 0
[all …]
H A Dbranch-limits-fp-mips.mir75 ; MIPS: $zero = SLL $zero, 0
80 ; MIPS: $zero = SLL $zero, 0
96 ; PIC: $zero = SLL $zero, 0
179 ; MIPS: $zero = SLL $zero, 0
184 ; MIPS: $zero = SLL $zero, 0
200 ; PIC: $zero = SLL $zero, 0
H A Dbranch-limits-msa.mir266 ; MSA: $zero = SLL $zero, 0
271 ; MSA: $zero = SLL $zero, 0
291 ; PIC: $zero = SLL $zero, 0
382 ; MSA: $zero = SLL $zero, 0
387 ; MSA: $zero = SLL $zero, 0
406 ; PIC: $zero = SLL $zero, 0
496 ; MSA: $zero = SLL $zero, 0
501 ; MSA: $zero = SLL $zero, 0
520 ; PIC: $zero = SLL $zero, 0
609 ; MSA: $zero = SLL $zero, 0
[all …]
H A Dbranch-limits-fp-mipsr6.mir77 ; R6: $zero = SLL $zero, 0
96 ; PIC: $zero = SLL $zero, 0
177 ; R6: $zero = SLL $zero, 0
196 ; PIC: $zero = SLL $zero, 0
H A Dbranch-limits-int-mips64r6.mir349 ; MIPS64: $zero = SLL $zero, 0
447 ; MIPS64: $zero = SLL $zero, 0
545 ; MIPS64: $zero = SLL $zero, 0
643 ; MIPS64: $zero = SLL $zero, 0
741 ; MIPS64: $zero = SLL $zero, 0
839 ; MIPS64: $zero = SLL $zero, 0
937 ; MIPS64: $zero = SLL $zero, 0
1035 ; MIPS64: $zero = SLL $zero, 0
1133 ; MIPS64: $zero = SLL $zero, 0
1231 ; MIPS64: $zero = SLL $zero, 0
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp48 AddInstr(SeqLs, Inst(SLL, Shamt)); in GetInstSeqLsSLL()
93 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) in ReplaceADDiuSLLWithLUi()
136 SLL = Mips::SLL; in Analyze()
141 SLL = Mips::DSLL; in Analyze()
H A DMipsAnalyzeImmediate.h60 unsigned ADDiu, ORi, SLL, LUi; variable
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp75 unsigned ORi, LUi, SLL; in loadImmediate() local
79 SLL = Mips::SLL; in loadImmediate()
84 SLL = Mips::SLL64_64; in loadImmediate()
107 MCInstBuilder(SLL) in loadImmediate()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Ddelay-slot-filler-bundled-insts-def-use.mir66 ; CHECK: renamable $at = SLL renamable $a0, 0, implicit killed $a0_64
75 ; CHECK: $zero = SLL $zero, 0
79 ; CHECK: $zero = SLL $zero, 0
86 renamable $at = SLL renamable $a0, 0, implicit killed $a0_64
H A Ddelay-slot-filler-bundled-insts.mir98 ; CHECK: $zero = SLL $zero, 0
103 ; CHECK: $zero = SLL $zero, 0
106 ; CHECK: $zero = SLL $zero, 0
H A Dload-store-left-right.ll16 %struct.SLL = type { i64 }
20 @sll = common global %struct.SLL zeroinitializer, align 1
121 %0 = load i64, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1
238 store i64 %a, i64* getelementptr inbounds (%struct.SLL, %struct.SLL* @sll, i64 0, i32 0), align 1
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Djump_table_and_brjt.mir93 ; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
94 ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]
121 ; MIPS32: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
160 ; MIPS32_PIC: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
161 ; MIPS32_PIC: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]
189 ; MIPS32_PIC: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
H A Dbitwise.mir247 ; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[COPY]], 1
248 ; MIPS32: $v0 = COPY [[SLL]]
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/Mips/
H A DTargetTest.cpp58 const unsigned SLL = IsGPR32 ? Mips::SLL : Mips::SLL64_64; in IsShift() local
59 return AllOf(OpcodeIs(SLL), in IsShift()
/llvm-project-15.0.7/llvm/test/CodeGen/BPF/
H A D32-bit-subreg-peephole-phi-1.ll3 ; For the below test case, 'b' in 'ret == b' needs SLL/SLR.
4 ; 'ret' in 'ret == b' does not need SLL/SLR as all 'ret' values
H A D32-bit-subreg-peephole-phi-2.ll4 ; need SLL/SLR. For 'ret', 'ret = a' may receive the value
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dshift-09.ll6 ; Check that we use SLLK over SLL where useful.
17 ; Check that we use SLL over SLLK where possible.
H A Dshift-01.ll6 ; Check the low end of the SLL range.
16 ; Check the high end of the defined SLL range.
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A Dvalid.s112 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
115 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
118 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
121 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dvalid.s148 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
151 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
154 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
157 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dxcore-stringtype.c33 long long LL, unsigned long long ULL, signed long long SLL, in builtinType() argument
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dvalid.s214 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
217 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
220 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
223 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32/
H A Dvalid.s210 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
213 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
216 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
219 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
/llvm-project-15.0.7/llvm/test/MC/Mips/mips32r5/
H A Dvalid.s259 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
262 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
265 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
268 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL

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