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/llvm-project-15.0.7/llvm/test/tools/llvm-rc/Inputs/
H A Dtag-accelerators.rc44 42, 5, VIRTKEY, SHIFT
47 42, 8, VIRTKEY, NOINVERT, SHIFT
49 42, 10, VIRTKEY, CONTROL, SHIFT
51 42, 12, VIRTKEY, SHIFT, ALT
62 "f", 23, VIRTKEY, SHIFT
67 "f", 28, VIRTKEY, CONTROL, SHIFT
69 "f", 30, VIRTKEY, SHIFT, ALT
80 "U", 41, VIRTKEY, SHIFT
87 "U", 48, VIRTKEY, SHIFT, ALT
98 "7", 59, VIRTKEY, SHIFT
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dshift-mask.ll55 ; X64-SHIFT: # %bb.0:
60 ; X64-SHIFT-NEXT: retq
83 ; X64-SHIFT: # %bb.0:
88 ; X64-SHIFT-NEXT: retq
136 ; X64-SHIFT-NEXT: retq
165 ; X64-SHIFT-NEXT: retq
208 ; X64-SHIFT-NEXT: retq
234 ; X64-SHIFT-NEXT: retq
279 ; X64-SHIFT-NEXT: retq
306 ; X64-SHIFT-NEXT: retq
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Datomicrmw-xchg-01.ll27 ; CHECK-SHIFT-LABEL: f1:
28 ; CHECK-SHIFT-NOT: %r3
29 ; CHECK-SHIFT: sll %r2, 3
30 ; CHECK-SHIFT-NOT: %r3
32 ; CHECK-SHIFT-NOT: %r3
33 ; CHECK-SHIFT: rll
34 ; CHECK-SHIFT-NOT: %r3
37 ; CHECK-SHIFT: rll
38 ; CHECK-SHIFT: br %r14
51 ; CHECK-SHIFT-LABEL: f2:
[all …]
H A Datomicrmw-xchg-02.ll27 ; CHECK-SHIFT-LABEL: f1:
28 ; CHECK-SHIFT-NOT: %r3
29 ; CHECK-SHIFT: sll %r2, 3
30 ; CHECK-SHIFT-NOT: %r3
32 ; CHECK-SHIFT-NOT: %r3
33 ; CHECK-SHIFT: rll
34 ; CHECK-SHIFT-NOT: %r3
37 ; CHECK-SHIFT: rll
38 ; CHECK-SHIFT: br %r14
51 ; CHECK-SHIFT-LABEL: f2:
[all …]
H A Dcmpxchg-01.ll31 ; CHECK-SHIFT-LABEL: f1:
32 ; CHECK-SHIFT: sll [[SHIFT:%r[1-9]+]], 3
33 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
34 ; CHECK-SHIFT: rll
50 ; CHECK-SHIFT-LABEL: f2:
53 ; CHECK-SHIFT: br %r14
83 ; CHECK-SHIFT: sll [[SHIFT:%r[1-9]+]], 3
84 ; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
85 ; CHECK-SHIFT: rll
121 ; CHECK-SHIFT: rll
[all …]
H A Dcmpxchg-02.ll31 ; CHECK-SHIFT-LABEL: f1:
32 ; CHECK-SHIFT: sll %r3, 3
34 ; CHECK-SHIFT: rll
50 ; CHECK-SHIFT-LABEL: f2:
53 ; CHECK-SHIFT: br %r14
82 ; CHECK-SHIFT-LABEL: f3:
83 ; CHECK-SHIFT: sll %r3, 3
85 ; CHECK-SHIFT: rll
117 ; CHECK-SHIFT-LABEL: f4:
120 ; CHECK-SHIFT: rll
[all …]
H A Datomicrmw-add-01.ll18 ; CHECK-DAG: sll [[SHIFT:%r[0-9]+]], 3
21 ; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]])
26 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
30 ; CHECK-SHIFT1: sll [[SHIFT:%r[1-9]+]], 3
31 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
60 ; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
64 ; CHECK-SHIFT1: sll [[SHIFT:%r[1-9]+]], 3
65 ; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DAMDHSAKernelDescriptor.h29 #define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) \ argument
30 NAME ## _SHIFT = (SHIFT), \
32 NAME = (((1 << (WIDTH)) - 1) << (SHIFT))
75 #define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \ argument
76 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)
100 #define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \ argument
101 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)
127 #define COMPUTE_PGM_RSRC3_GFX90A(NAME, SHIFT, WIDTH) \ argument
139 #define COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH) \ argument
152 #define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) \ argument
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsdwa-gfx9.mir8 # CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
9 # CI: %{{[0-9]+}}:vgpr_32 = V_ADD_CO_U32_e32 [[SMOV]], killed [[SHIFT]], implicit-def $vcc, implici…
52 # CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
53 # CI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit $mode, implicit $ex…
55 # VI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
56 # VI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit $mode, implicit $ex…
H A Ddivergence-driven-buildvector.ll69 ; GCN: %[[SHIFT:[0-9]+]]:sreg_32 = S_MOV_B32 16
70 ; GCN: %[[SHL:[0-9]+]]:sreg_32 = S_LSHL_B32 killed %{{[0-9]+}}, killed %[[SHIFT]]
88 ; GCN: %[[SHIFT:[0-9]+]]:sreg_32 = S_MOV_B32 16
89 ; GCN: %[[SHL:[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 killed %[[SHIFT]], %1, implicit $exec
137 ; GCN: %[[SHIFT:[0-9]+]]:sreg_32 = S_MOV_B32 16
138 ; GCN: %[[SHR:[0-9]+]]:sreg_32 = S_LSHR_B32 killed %{{[0-9]+}}, killed %[[SHIFT]]
181 ; GCN: %[[SHIFT:[0-9]+]]:sreg_32 = S_MOV_B32 16
182 ; GCN: %[[SHL:[0-9]+]]:sreg_32 = S_LSHL_B32 killed %{{[0-9]+}}, killed %[[SHIFT]]
203 ; GCN: %[[SHIFT:[0-9]+]]:sreg_32 = S_MOV_B32 16
204 ; GCN: %[[SHL:[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 killed %[[SHIFT]]
H A Dbfe-combine.ll8 ; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
9 ; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unuse…
29 ; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 15
30 ; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE1:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unus…
H A Dframe-index-elimination.ll122 ; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], s32, 6
123 ; CI-NEXT: v_or_b32_e32 v0, 4, [[SHIFT]]
125 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
126 ; GFX9-MUBUF-NEXT: v_or_b32_e32 v0, 4, [[SHIFT]]
165 ; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], s32, 6
166 ; CI: v_add_i32_e32 [[GEP:v[0-9]+]], vcc, 4, [[SHIFT]]
282 ; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], s32, 6
283 ; CI-NEXT: v_or_b32_e32 [[PTR:v[0-9]+]], 4, [[SHIFT]]
285 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, s32
286 ; GFX9-MUBUF-NEXT: v_or_b32_e32 [[PTR:v[0-9]+]], 4, [[SHIFT]]
H A Dsdwa-scalar-ops.mir5 # GCN: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
8 # GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD …
9 # GCN: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD …
12 # VI: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
15 # VI: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD s…
16 # VI: v_lshlrev_b32_sdwa v{{[0-9]+}}, v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD s…
18 # GFX9: s_mov_b32 s[[SHIFT:[0-9]+]], 2
21 # GFX9: v_lshlrev_b32_sdwa v{{[0-9]+}}, s[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD…
22 # GFX9: v_lshlrev_b32_sdwa v{{[0-9]+}}, s[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD…
/llvm-project-15.0.7/libc/AOR_v20.02/math/
H A Dexp2f.c26 #define SHIFT __exp2f_data.shift_scaled macro
62 kd = eval_as_double (xd + SHIFT); in exp2f()
64 kd -= SHIFT; /* k/N for int k. */ in exp2f()
H A Dexpf.c71 # define SHIFT __exp2f_data.shift in expf() macro
72 kd = eval_as_double (z + SHIFT); in expf()
74 kd -= SHIFT; in expf()
H A Dpowf.c88 # define SHIFT __exp2f_data.shift_scaled in exp2_inline() macro
90 kd = eval_as_double (xd + SHIFT); in exp2_inline()
92 kd -= SHIFT; /* k/N */ in exp2_inline()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dnegated-bitmask.ll119 ; CHECK-NEXT: [[SHIFT:%.*]] = lshr i8 [[A0:%.*]], 3
120 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SHIFT]], 2
144 ; CHECK-NEXT: [[SHIFT:%.*]] = lshr <2 x i32> [[A0:%.*]], [[A1:%.*]]
145 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHIFT]], <i32 1, i32 1>
158 ; CHECK-NEXT: [[SHIFT:%.*]] = lshr i8 [[A0:%.*]], 3
159 ; CHECK-NEXT: [[MASK:%.*]] = and i8 [[SHIFT]], 1
174 ; CHECK-NEXT: [[SHIFT:%.*]] = lshr <2 x i32> [[A0:%.*]], <i32 3, i32 3>
175 ; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHIFT]], <i32 1, i32 1>
177 ; CHECK-NEXT: call void @usev2i32(<2 x i32> [[SHIFT]])
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/X86/
H A Dextract-binop.ll263 ; AVX-NEXT: [[TMP1:%.*]] = add nuw <16 x i8> [[X:%.*]], [[SHIFT]]
301 ; AVX-NEXT: [[TMP1:%.*]] = and <16 x i8> [[X:%.*]], [[SHIFT]]
314 ; CHECK-NEXT: [[TMP1:%.*]] = fmul <4 x float> [[SHIFT]], [[X]]
364 ; AVX-NEXT: [[TMP1:%.*]] = fadd <8 x float> [[X]], [[SHIFT]]
383 ; AVX-NEXT: [[TMP1:%.*]] = fadd <8 x float> [[SHIFT]], [[X]]
422 ; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[SHIFT]], [[A]]
440 ; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[A]], [[SHIFT]]
459 ; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[A]], [[SHIFT]]
496 ; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[Z]], [[SHIFT]]
518 ; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[SHIFT]], [[X]]
[all …]
H A Dextract-binop-inseltpoison.ll263 ; AVX-NEXT: [[TMP1:%.*]] = add nuw <16 x i8> [[X:%.*]], [[SHIFT]]
301 ; AVX-NEXT: [[TMP1:%.*]] = and <16 x i8> [[X:%.*]], [[SHIFT]]
314 ; CHECK-NEXT: [[TMP1:%.*]] = fmul <4 x float> [[SHIFT]], [[X]]
364 ; AVX-NEXT: [[TMP1:%.*]] = fadd <8 x float> [[X]], [[SHIFT]]
383 ; AVX-NEXT: [[TMP1:%.*]] = fadd <8 x float> [[SHIFT]], [[X]]
422 ; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[SHIFT]], [[A]]
440 ; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[A]], [[SHIFT]]
459 ; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[A]], [[SHIFT]]
496 ; CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[Z]], [[SHIFT]]
518 ; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[SHIFT]], [[X]]
[all …]
H A Dextract-cmp-binop.ll16 ; AVX-NEXT: [[SHIFT:%.*]] = shufflevector <2 x i1> [[TMP1]], <2 x i1> poison, <2 x i32> <i32 1, …
17 ; AVX-NEXT: [[TMP2:%.*]] = and <2 x i1> [[TMP1]], [[SHIFT]]
40 ; AVX-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i1> [[TMP1]], <4 x i1> poison, <4 x i32> <i32 2, …
41 ; AVX-NEXT: [[TMP2:%.*]] = or <4 x i1> [[TMP1]], [[SHIFT]]
56 ; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i1> [[TMP1]], <4 x i1> poison, <4 x i32> <i32 u…
57 ; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i1> [[TMP1]], [[SHIFT]]
82 ; AVX-NEXT: [[SHIFT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> poison, <8 x i32> <i32 und…
83 ; AVX-NEXT: [[TMP2:%.*]] = add <8 x i1> [[TMP1]], [[SHIFT]]
H A Dextract-cmp.ll112 ; AVX-NEXT: [[SHIFT:%.*]] = shufflevector <2 x double> [[Y:%.*]], <2 x double> poison, <2 x i32>…
113 ; AVX-NEXT: [[TMP1:%.*]] = fcmp oge <2 x double> [[X:%.*]], [[SHIFT]]
131 ; AVX-NEXT: [[SHIFT:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> poison, <2 x i32>…
132 ; AVX-NEXT: [[TMP1:%.*]] = fcmp ule <2 x double> [[SHIFT]], [[Y:%.*]]
144 ; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> poison, <4 x i32> <i3…
145 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[SHIFT]]
164 ; AVX-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> poison, <4 x i32> <…
165 ; AVX-NEXT: [[TMP1:%.*]] = fcmp ugt <4 x float> [[A]], [[SHIFT]]
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/COFF/Inputs/resources/
H A Dtest_resource.rc8 "D", 1100, VIRTKEY, CONTROL, SHIFT
34 "H", 5678, VIRTKEY, CONTROL, SHIFT
/llvm-project-15.0.7/clang/test/Sema/
H A Dwarn-int-in-bool-context.c9 #define SHIFT(l, r) l << r macro
73 return SHIFT(1, a); in test()
/llvm-project-15.0.7/llvm/test/tools/llvm-cvtres/Inputs/
H A Dtest_resource.rc8 "D", 1100, VIRTKEY, CONTROL, SHIFT
34 "H", 5678, VIRTKEY, CONTROL, SHIFT
/llvm-project-15.0.7/lld/test/COFF/Inputs/
H A Dcombined-resources.rc8 "D", 1100, VIRTKEY, CONTROL, SHIFT
34 "H", 5678, VIRTKEY, CONTROL, SHIFT

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