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Searched refs:SHFL (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/mlir/test/Conversion/GPUToNVVM/
H A Dgpu-to-nvvm.mlir133 …// CHECK: %[[#SHFL:]] = nvvm.shfl.sync bfly %[[#MASK]], %[[#VALUE]], %[[#OFFSET]], %[[#CLAMP]] {re…
134 // CHECK: llvm.extractvalue %[[#SHFL]][0 : index] : !llvm.struct<(f32, i1)>
135 // CHECK: llvm.extractvalue %[[#SHFL]][1 : index] : !llvm.struct<(f32, i1)>
142 …// CHECK: %[[#SHFL:]] = nvvm.shfl.sync up %[[#MASK]], %[[#VALUE]], %[[#OFFSET]], %[[#NUM_LANES]] {…
143 // CHECK: llvm.extractvalue %[[#SHFL]][0 : index] : !llvm.struct<(f32, i1)>
144 // CHECK: llvm.extractvalue %[[#SHFL]][1 : index] : !llvm.struct<(f32, i1)>
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h128 SHFL, enumerator
H A DRISCVInstrInfoZb.td50 def riscv_shfl : SDNode<"RISCVISD::SHFL", SDTIntBinOp>;
415 def SHFL : ALU_rr<0b0000100, 0b001, "shfl">,
914 def : PatGprGpr<riscv_shfl, SHFL>;
H A DRISCVISelLowering.cpp4869 IntNo == Intrinsic::riscv_zip ? RISCVISD::SHFL : RISCVISD::UNSHFL; in LowerINTRINSIC_WO_CHAIN()
4878 IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL; in LowerINTRINSIC_WO_CHAIN()
7143 case RISCVISD::SHFL: { in ReplaceNodeResults()
7332 IntNo == Intrinsic::riscv_shfl ? RISCVISD::SHFL : RISCVISD::UNSHFL; in ReplaceNodeResults()
7802 return DAG.getNode(RISCVISD::SHFL, DL, VT, Match1->Op, in combineORToSHFL()
8139 if (auto SHFL = combineORToSHFL(SDValue(N, 0), DAG, Subtarget)) in performORCombine() local
8140 return SHFL; in performORCombine()
8937 case RISCVISD::SHFL: in PerformDAGCombine()
9690 case RISCVISD::SHFL: in ComputeNumSignBitsForTargetNode()
11650 NODE_NAME_CASE(SHFL) in getTargetNodeName()