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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dbinop-cast.ll50 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[Y:%.*]] to i32
51 ; CHECK-NEXT: call void @use(i32 [[SEXT]])
52 ; CHECK-NEXT: [[R:%.*]] = and i32 [[SEXT]], [[X:%.*]]
63 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 [[Y:%.*]] to i32
64 ; CHECK-NEXT: call void @use(i32 [[SEXT]])
109 ; CHECK-NEXT: call void @use(i32 [[SEXT]])
110 ; CHECK-NEXT: [[R:%.*]] = or i32 [[SEXT]], [[X:%.*]]
122 ; CHECK-NEXT: call void @use(i32 [[SEXT]])
170 ; CHECK-NEXT: call void @use(i32 [[SEXT]])
183 ; CHECK-NEXT: call void @use(i32 [[SEXT]])
[all …]
H A Dsignext.ll10 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 16
11 ; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 16
37 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[X:%.*]], <i32 16, i32 16>
38 ; CHECK-NEXT: [[T3:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 16, i32 16>
49 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 16
50 ; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 16
61 ; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[X:%.*]], <i32 16, i32 16>
62 ; CHECK-NEXT: [[T3:%.*]] = ashr exact <2 x i32> [[SEXT]], <i32 16, i32 16>
110 ; CHECK-NEXT: [[SEXT:%.*]] = shl i32 [[X:%.*]], 24
111 ; CHECK-NEXT: [[T3:%.*]] = ashr exact i32 [[SEXT]], 24
[all …]
H A Dsext.ll210 ; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i1> [[CMP]] to <2 x i16>
211 ; CHECK-NEXT: store <2 x i16> [[SEXT]], <2 x i16>* [[DST:%.*]], align 4
238 ; CHECK-NEXT: [[SEXT:%.*]] = add nsw i32 [[TMP1]], -1
239 ; CHECK-NEXT: ret i32 [[SEXT]]
251 ; CHECK-NEXT: [[SEXT:%.*]] = add nsw i16 [[TMP1]], -1
252 ; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
264 ; CHECK-NEXT: [[SEXT:%.*]] = ashr i32 [[AND]], 31
265 ; CHECK-NEXT: ret i32 [[SEXT]]
276 ; CHECK-NEXT: [[SEXT:%.*]] = ashr i16 [[AND]], 15
277 ; CHECK-NEXT: [[EXT:%.*]] = sext i16 [[SEXT]] to i32
H A Dreduction-xor-sext-zext-i1.ll21 ; CHECK-NEXT: [[SEXT:%.*]] = sub nsw i4 0, [[TMP3]]
22 ; CHECK-NEXT: [[TMP4:%.*]] = sext i4 [[SEXT]] to i32
48 ; CHECK-NEXT: [[SEXT:%.*]] = sub nsw i16 0, [[TMP3]]
49 ; CHECK-NEXT: ret i16 [[SEXT]]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dcmp_ext.ll6 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
8 ; CHECK-NEXT: [[CMP:%.*]] = icmp uge i64 [[ZEXT]], [[SEXT]]
29 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
62 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
85 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
108 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
131 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
144 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
167 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
210 ; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[X:%.*]] to i64
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Dshift-ops-to-llvm.mlir15 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32
16 // CHECK: llvm.ashr %{{.*}}, %[[SEXT]] : i32
33 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64>
34 // CHECK: llvm.ashr %{{.*}}, %[[SEXT]] : vector<4xi64>
55 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32
56 // CHECK: llvm.lshr %{{.*}}, %[[SEXT]] : i32
73 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : vector<4xi32> to vector<4xi64>
74 // CHECK: llvm.lshr %{{.*}}, %[[SEXT]] : vector<4xi64>
95 // CHECK: %[[SEXT:.*]] = llvm.sext %{{.*}} : i16 to i32
96 // CHECK: llvm.shl %{{.*}}, %[[SEXT]] : i32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-sextload-flat.mir82 ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
83 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
89 ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
90 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
106 ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
107 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
114 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
130 ; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
131 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
137 ; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
[all …]
H A Dregbankselect-sext.mir16 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[COPY]](s32)
33 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[TRUNC]](s16)
72 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s16) = G_SEXT [[TRUNC]](s1)
93 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s1)
114 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[TRUNC]](s1)
202 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s16) = G_SEXT [[TRUNC]](s1)
220 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s1)
238 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[TRUNC]](s1)
256 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vgpr(s16) = G_SEXT [[TRUNC]](s1)
274 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:vgpr(s32) = G_SEXT [[TRUNC]](s1)
[all …]
H A Dlegalize-sextload-local.mir64 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
65 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
81 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
82 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
98 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
99 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
H A Dlegalize-sextload-private.mir66 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
67 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
83 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
84 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
100 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
101 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
H A Dlegalize-sextload-constant-32bit.mir18 ; CI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
19 ; CI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
38 ; CI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
39 ; CI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
58 ; CI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
59 ; CI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
H A Dlegalize-icmp.mir454 ; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
462 ; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
470 ; GFX9-NEXT: $vgpr0 = COPY [[SEXT]](s32)
490 ; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
498 ; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
506 ; GFX9-NEXT: $vgpr0 = COPY [[SEXT]](s32)
527 ; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
535 ; GFX8-NEXT: $vgpr0 = COPY [[SEXT]](s32)
543 ; GFX9-NEXT: $vgpr0 = COPY [[SEXT]](s32)
564 ; GFX7-NEXT: $vgpr0 = COPY [[SEXT]](s32)
[all …]
H A Dlegalize-sextload-global.mir231 ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
238 ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
255 ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
262 ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
278 ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
279 ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
285 ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
286 ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
333 ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
345 ; GFX6-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[OR]](s32)
[all …]
H A Dlegalize-smulo.mir21 ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
23 ; GFX8-NEXT: $vgpr1 = COPY [[SEXT]](s32)
34 ; GFX9-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
36 ; GFX9-NEXT: $vgpr1 = COPY [[SEXT]](s32)
124 ; GFX8-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ICMP]](s1)
126 ; GFX8-NEXT: $vgpr1 = COPY [[SEXT]](s32)
140 ; GFX9-NEXT: $vgpr1 = COPY [[SEXT]](s32)
171 ; GFX8-NEXT: $vgpr1 = COPY [[SEXT]](s32)
185 ; GFX9-NEXT: $vgpr1 = COPY [[SEXT]](s32)
498 ; GFX8-NEXT: $vgpr1 = COPY [[SEXT]](s32)
[all …]
H A Dirtranslator-struct-return-intrinsics.ll16 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[INT1]](s1)
18 …; CHECK-NEXT: G_STORE [[SEXT]](s32), [[COPY2]](p1) :: (store (s32) into `i32 addrspace(1)* undef…
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Darm64-irtranslator-gep.ll14 ; O0-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
16 ; O0-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
20 ; O0-NEXT: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C]]
35 ; O3-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
37 ; O3-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SEXT]], [[C1]]
41 ; O3-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[SEXT]], [[C]](s64)
H A Dcombine-ext.mir64 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
65 ; CHECK: $x0 = COPY [[SEXT]](s64)
78 ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s16>)
79 ; CHECK: $q0 = COPY [[SEXT]](<2 x s64>)
120 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
121 ; CHECK: $x0 = COPY [[SEXT]](s64)
134 ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s16>)
135 ; CHECK: $q0 = COPY [[SEXT]](<2 x s64>)
H A Dirtranslator-one-by-n-vector-ptr-add.ll16 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
17 ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](s64)
35 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
36 ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[SEXT]](s64)
H A Dlegalize-sext-copy.mir13 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
14 ; CHECK: $x0 = COPY [[SEXT]](s64)
H A Dlegalize-rotr-rotl.mir14 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
15 ; CHECK: %rot:_(s32) = G_ROTR [[COPY]], [[SEXT]](s64)
59 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SUB]](s32)
60 ; CHECK: %rot:_(s32) = G_ROTR [[COPY]], [[SEXT]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsint_to_fp.f64.ll76 ; CI: s_sext_i32_i8 [[SEXT:s[0-9]+]], [[VAL]]
79 ; VI: s_sext_i32_i16 [[SEXT:s[0-9]+]], [[BFE]]
81 ; GCN: v_cvt_f64_i32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[SEXT]]
89 ; GCN: v_bfe_i32 [[SEXT:v[0-9]+]]
90 ; GCN: v_cvt_f64_i32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[SEXT]]
/llvm-project-15.0.7/llvm/test/Instrumentation/InstrProfiling/
H A Dicall-comdat.ll9 …-unknown-linux -passes=instrprof -vp-static-alloc=true -S | FileCheck %s --check-prefix=STATIC-SEXT
10 …-unknown-linux -passes=instrprof -vp-static-alloc=true -S | FileCheck %s --check-prefix=STATIC-SEXT
60 ; STATIC-SEXT: call void @__llvm_profile_instrument_target(i64 %3, ptr @__profd_foo, i32 signext 0)
64 ; STATIC-SEXT: declare void @__llvm_profile_instrument_target(i64, ptr, i32 signext)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-ext.mir371 ; X32: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
372 ; X32: $ax = COPY [[SEXT]](s16)
376 ; X64: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[COPY]](s8)
377 ; X64: $ax = COPY [[SEXT]](s16)
399 ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
400 ; X32: $eax = COPY [[SEXT]](s32)
404 ; X64: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s8)
405 ; X64: $eax = COPY [[SEXT]](s32)
427 ; X32: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY]](s16)
428 ; X32: $eax = COPY [[SEXT]](s32)
[all …]
H A Dlegalize-ext-x86-64.mir108 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s8)
109 ; CHECK: $rax = COPY [[SEXT]](s64)
131 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s16)
132 ; CHECK: $rax = COPY [[SEXT]](s64)
154 ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
155 ; CHECK: $rax = COPY [[SEXT]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Daarch64-codegen-prepare-atp.ll50 ; CHECK: %[[SEXT:.*]] = sext i32 %i to i64
51 ; CHECK: %add = add nsw i64 %[[SEXT]], 1
52 ; CHECK: %add2 = add nsw i64 %[[SEXT]], 2

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