| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | aarch64-neon-v1i1-setcc.ll | 4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
6 ; As the v1i64 operands of SETCC are legal types, they will not be scalarized.
8 ; operands of SETCC have been legalized.
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
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| /llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/ |
| H A D | sdiv-minsigned.ll | 4 ; This checks for a bug in the DAG combiner where a SETCC was created with
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| H A D | isel-setcc-legalize-loop.ll | 4 ; due to the repeated split-widen operations in legalizing SETCC.
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| /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/ |
| H A D | int-cmp-54.ll | 1 ; Check that custom handling of SETCC does not crash
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| H A D | setcc-01.ll | 1 ; Test SETCC for every integer condition. The tests here assume that
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| H A D | setcc-03.ll | 1 ; Test SETCC with an i32 result for every integer condition.
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| H A D | setcc-04.ll | 1 ; Test SETCC with an i64 result for every floating-point condition.
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| H A D | setcc-02.ll | 1 ; Test SETCC for every floating-point condition. The tests here assume that
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | avx512-adc-sbb.ll | 4 ; This asserted because we didn't account for a zext of a non-SETCC node:
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| H A D | avx512-vec3-crash.ll | 4 ; This test crashed during type legalization of SETCC result type.
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| H A D | optimize-compare.mir | 395 ; CMP+SETCC %0 == 1
398 ; CMP+SETCC %0 >= 2; CMP can be removed.
422 ; CMP+SETCC %0 != 42
425 ; CMP+SETCC %0 >= 2; CMP can be removed.
492 ; CMP+SETCC %0 <s 1
522 ; CMP+SETCC %0 == INT32_MAX
571 ; CMP+SETCC %0 == INT16_MIN
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.h | 185 static inline bool IsSETCC(unsigned SETCC) { in IsSETCC() argument
186 switch (SETCC) { in IsSETCC()
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| H A D | M68kISelLowering.cpp | 130 setOperationAction(ISD::SETCC, VT, Custom); in M68kTargetLowering()
1333 case ISD::SETCC: in LowerOperation()
1440 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in getBitTestCondition()
1942 if (Op0.getOpcode() == M68kISD::SETCC) { in LowerSETCC()
1974 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
2038 if (Cond.getOpcode() == ISD::SETCC) { in LowerSELECT()
2047 if (Cond.getOpcode() == M68kISD::SETCC && in LowerSELECT()
2262 if (Cond.getOpcode() == ISD::SETCC) { in LowerBRCOND()
3370 if (Carry.getOpcode() == M68kISD::SETCC || in combineCarryThroughADD()
3457 case M68kISD::SETCC: in PerformDAGCombine()
[all …]
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| H A D | M68kISelLowering.h | 53 SETCC, enumerator
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 2696 { ISD::SETCC, MVT::v2i64, 2 }, in getCmpSelInstrCost()
2700 { ISD::SETCC, MVT::v32i16, 1 }, in getCmpSelInstrCost()
2701 { ISD::SETCC, MVT::v64i8, 1 }, in getCmpSelInstrCost()
2708 { ISD::SETCC, MVT::v8i64, 1 }, in getCmpSelInstrCost()
2709 { ISD::SETCC, MVT::v16i32, 1 }, in getCmpSelInstrCost()
2710 { ISD::SETCC, MVT::v8f64, 1 }, in getCmpSelInstrCost()
2711 { ISD::SETCC, MVT::v16f32, 1 }, in getCmpSelInstrCost()
2740 { ISD::SETCC, MVT::v4i64, 1 }, in getCmpSelInstrCost()
2741 { ISD::SETCC, MVT::v8i32, 1 }, in getCmpSelInstrCost()
2742 { ISD::SETCC, MVT::v16i16, 1 }, in getCmpSelInstrCost()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.h | 41 SETCC, enumerator
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| H A D | LanaiISelLowering.cpp | 88 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
188 case ISD::SETCC: in LowerOperation()
985 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag); in LowerSETCC()
1109 case LanaiISD::SETCC: in getTargetNodeName()
1499 case LanaiISD::SETCC: in computeKnownBitsForTargetNode()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.h | 54 SETCC, enumerator
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| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | pr24636.ll | 12 ; We used to crash because a bad DAGCombine was creating i32-typed SETCC nodes,
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 119 ADD_VVP_OP(VVP_SETCC, SETCC)
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 65 // Both of these match to FCmp / SETCC.
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 736 SETCC, enumerator
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 478 if (Cond->getOpcode() == ISD::SETCC) { in ScalarizeVecRes_VSELECT()
665 case ISD::SETCC: in ScalarizeVectorOperand()
985 case ISD::SETCC: in SplitVectorResult()
1868 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_VP_LOAD()
1942 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_MLOAD()
2121 if (N->getOpcode() == ISD::SETCC) { in SplitVecRes_SETCC()
3132 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) { in SplitVecOp_VP_STORE()
3210 if (OpNo == 1 && Mask.getOpcode() == ISD::SETCC) { in SplitVecOp_MSTORE()
3534 if (N->getOpcode() == ISD::SETCC) { in SplitVecOp_VSETCC()
5012 case ISD::SETCC: in isSETCCOp()
[all …]
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| H A D | LegalizeVectorOps.cpp | 451 case ISD::SETCC: { in LegalizeOp()
745 DAG.getNode(ISD::SETCC, SDLoc(Node), CondVT, Node->getOperand(0), in Expand()
766 case ISD::SETCC: in Expand()
1480 LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC, in ExpandSETCC()
1643 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/ |
| H A D | constant-folding-crash.ll | 8 ; BUILD_VECTOR) created a (v4i1 = SETCC v4i8) which during constant-folding
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