Home
last modified time | relevance | path

Searched refs:SELECT (Results 1 – 25 of 186) sorted by relevance

12345678

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dpostlegalizer-lowering-swap-compare-operands.mir31 ; SELECT: liveins: $x0, $x1
38 ; SELECT: $w0 = COPY %cmp
68 ; SELECT: liveins: $x0, $x1
74 ; SELECT: $w0 = COPY %cmp2
112 ; SELECT: $w0 = COPY %cmp
149 ; SELECT: $w0 = COPY %cmp
183 ; SELECT: $w0 = COPY %cmp
220 ; SELECT: $w0 = COPY %cmp
257 ; SELECT: $w0 = COPY %cmp
296 ; SELECT: $w0 = COPY %cmp
[all …]
H A Dpostlegalizer-lowering-adjust-icmp-imm.mir30 ; SELECT: liveins: $w0
31 ; SELECT-NEXT: {{ $}}
66 ; SELECT: liveins: $x0
67 ; SELECT-NEXT: {{ $}}
102 ; SELECT: liveins: $w0
103 ; SELECT-NEXT: {{ $}}
138 ; SELECT: liveins: $x0
139 ; SELECT-NEXT: {{ $}}
174 ; SELECT: liveins: $w0
175 ; SELECT-NEXT: {{ $}}
[all …]
H A Dpostlegalizer-lowering-build-vector-to-dup.mir18 ; SELECT-LABEL: name: same_reg
19 ; SELECT: liveins: $d0
20 ; SELECT: %r:gpr32 = IMPLICIT_DEF
47 ; SELECT: %q:gpr32 = COPY $w1
78 ; SELECT: liveins: $d0
106 ; SELECT: liveins: $d0
135 ; SELECT: liveins: $d0
136 ; SELECT: %v:fpr64 = COPY $d0
138 ; SELECT: $d0 = COPY %sub
168 ; SELECT: liveins: $d0, $d1
[all …]
H A Dlegalize-intrinsic-min-max.mir23 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
24 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
52 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
53 ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
81 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY]], [[COPY1]]
82 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
111 ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
142 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
171 ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
200 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
[all …]
H A Dregbank-select.mir21 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s32) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY2]]
22 ; CHECK-NEXT: $s0 = COPY [[SELECT]](s32)
48 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY2]]
49 ; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
81 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY2]]
82 ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
112 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:fpr(s64) = G_SELECT [[COPY]](s32), [[COPY1]], [[COPY3]]
113 ; CHECK-NEXT: $d0 = COPY [[SELECT]](s64)
143 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:gpr(s64) = G_SELECT [[COPY]](s32), [[COPY3]], [[COPY2]]
144 ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
[all …]
H A Dlegalize-usub-sat.mir23 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[C]], [[USUBO]]
24 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
53 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[C]], [[USUBO]]
54 ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
88 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
89 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
126 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
127 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
164 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[SUB]]
165 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
H A Dlegalize-uadd-sat.mir23 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[C]], [[UADDO]]
24 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
53 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[C]], [[UADDO]]
54 ; CHECK-NEXT: $x0 = COPY [[SELECT]](s64)
88 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[ADD]]
89 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
126 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[C1]], [[ADD]]
127 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
167 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND3]](s32), [[COPY2]], [[ADD]]
168 ; CHECK-NEXT: $w0 = COPY [[SELECT]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dselect-fabs-fneg-extract.ll10 ; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Z]]
105 ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Z]]
123 ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
155 ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[X]]
172 ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
192 ; GCN: v_add_f32_e32 v{{[0-9]+}}, [[SELECT]], [[Y]]
724 ; GCN-NEXT: buffer_store_dword [[SELECT]]
741 ; GCN-NEXT: buffer_store_dword [[SELECT]]
757 ; GCN-NEXT: buffer_store_dword [[SELECT]]
774 ; GCN-NEXT: buffer_store_dword [[SELECT]]
[all …]
H A Dselect-fabs-fneg-extract-legacy.ll11 ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[RCP]], vcc
12 ; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]]
29 ; GCN: v_cndmask_b32_e32 [[SELECT:v[0-9]+]], -2.0, [[MUL]], vcc
30 ; GCN: v_xor_b32_e32 [[NEG_SELECT:v[0-9]+]], 0x80000000, [[SELECT]]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dselect-gep.ll9 ; CHECK-NEXT: ret i32* [[SELECT]]
23 ; CHECK-NEXT: ret i32* [[SELECT]]
37 ; CHECK-NEXT: ret i32* [[SELECT]]
51 ; CHECK-NEXT: ret i32* [[SELECT]]
64 ; CHECK-NEXT: ret i32* [[SELECT]]
79 ; CHECK-NEXT: ret i32* [[SELECT]]
93 ; CHECK-NEXT: ret i32* [[SELECT]]
142 ; CHECK-NEXT: ret i32* [[SELECT]]
157 ; CHECK-NEXT: ret i32* [[SELECT]]
172 ; CHECK-NEXT: ret i32* [[SELECT]]
[all …]
H A Dselect-with-bitwise-ops.ll43 ; CHECK-NEXT: ret i32 [[SELECT]]
58 ; CHECK-NEXT: ret i32 [[SELECT]]
101 ; CHECK-NEXT: ret i32 [[SELECT]]
116 ; CHECK-NEXT: ret i32 [[SELECT]]
159 ; CHECK-NEXT: ret i32 [[SELECT]]
174 ; CHECK-NEXT: ret i32 [[SELECT]]
215 ; CHECK-NEXT: ret i32 [[SELECT]]
230 ; CHECK-NEXT: ret i32 [[SELECT]]
407 ; CHECK-NEXT: ret i8 [[SELECT]]
422 ; CHECK-NEXT: ret i8 [[SELECT]]
[all …]
H A Dxor-of-icmps-with-extra-uses.ll11 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0_INV]], i32 32767, i32 -32768
12 ; CHECK-NEXT: store i32 [[SELECT]], i32* [[SELECTED:%.*]], align 4
27 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0]], i32 -32768, i32 [[Y:%.*]]
28 ; CHECK-NEXT: store i32 [[SELECT]], i32* [[SELECTED:%.*]], align 4
43 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0_INV]], i32 32767, i32 [[Y:%.*]]
44 ; CHECK-NEXT: store i32 [[SELECT]], i32* [[SELECTED:%.*]], align 4
111 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0]], i32 [[Y:%.*]], i32 32767
113 ; CHECK-NEXT: store i32 [[SELECT]], i32* [[SELECTED:%.*]], align 4
133 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0]], i32 32767, i32 [[Y:%.*]]
135 ; CHECK-NEXT: store i32 [[SELECT]], i32* [[SELECTED:%.*]], align 4
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-select.mir21 ; FAST-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]]
58 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY3]]
344 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
389 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
433 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[UV]], [[UV2]]
475 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
515 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
555 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
595 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
804 ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]]
[all …]
H A Dlegalize-intrinsic-amdgcn-fdiv-fast.mir20 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
21 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY1]], [[SELECT]]
24 ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[SELECT]], [[FMUL1]]
48 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
49 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = nsz G_FMUL [[COPY1]], [[SELECT]]
52 ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = nsz G_FMUL [[SELECT]], [[FMUL1]]
H A Dlegalize-select.mir18 ; CHECK-NEXT: $vgpr0 = COPY [[SELECT]](s32)
44 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
70 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
376 ; CHECK-NEXT: $vgpr0 = COPY [[SELECT]](<2 x s16>)
631 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
657 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](p1)
683 ; CHECK-NEXT: $vgpr0 = COPY [[SELECT]](p2)
709 ; CHECK-NEXT: $vgpr0 = COPY [[SELECT]](p3)
735 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](p4)
762 ; CHECK-NEXT: $vgpr0 = COPY [[SELECT]](p5)
[all …]
H A Dlegalize-ushlsat.mir28 ; GFX6-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SELECT]], [[C1]](s32)
303 ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
389 ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT]](s16)
527 ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT]](s16)
702 ; GFX8-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[SELECT]](s16)
785 ; GFX6-NEXT: $vgpr0 = COPY [[SELECT]](s32)
796 ; GFX8-NEXT: $vgpr0 = COPY [[SELECT]](s32)
807 ; GFX9-NEXT: $vgpr0 = COPY [[SELECT]](s32)
897 ; GFX6-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
909 ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
[all …]
H A Dregbankselect-phi-s1.mir42 ; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
74 ; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
154 ; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
202 ; GREEDY-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
277 ; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
371 ; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
463 ; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
555 ; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
649 ; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
745 ; FAST-NEXT: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
[all …]
H A Dlegalize-sshlsat.mir29 ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[C3]]
51 ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[C3]]
74 ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[C3]]
110 ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[C3]]
132 ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[C3]]
155 ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C2]], [[C3]]
194 ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C3]], [[C4]]
237 ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C3]], [[C4]]
278 ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C3]], [[C4]]
350 ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s16) = G_SELECT [[ICMP]](s1), [[C]], [[C1]]
[all …]
H A Dlegalize-addrspacecast.mir225 ; VI-NEXT: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[ICMP]](s1), [[MV]], [[C2]]
226 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
240 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
270 ; VI-NEXT: $vgpr0 = COPY [[SELECT]](p5)
280 ; GFX9-NEXT: $vgpr0 = COPY [[SELECT]](p5)
290 ; SI-NEXT: $vgpr0 = COPY [[SELECT]](p5)
321 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
335 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](p0)
365 ; VI-NEXT: $vgpr0 = COPY [[SELECT]](p3)
375 ; GFX9-NEXT: $vgpr0 = COPY [[SELECT]](p3)
[all …]
H A Dlegalize-fcmp.mir19 ; GFX7-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
20 ; GFX7-NEXT: $vgpr0 = COPY [[SELECT]](s32)
27 ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C]], [[COPY]]
28 ; GFX8-NEXT: $vgpr0 = COPY [[SELECT]](s32)
36 ; GFX9-NEXT: $vgpr0 = COPY [[SELECT]](s32)
56 ; GFX7-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
64 ; GFX8-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
72 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[SELECT]](s64)
95 ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
105 ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SELECT]](s16)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dselect.mir30 ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
31 ; MIPS32: $v0 = COPY [[SELECT]](s32)
60 ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
61 ; MIPS32: $v0 = COPY [[SELECT]](s32)
91 ; MIPS32: $v0 = COPY [[SELECT]](s32)
117 ; MIPS32: [[SELECT:%[0-9]+]]:_(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
118 ; MIPS32: $v0 = COPY [[SELECT]](p0)
148 ; MIPS32: $v0 = COPY [[SELECT]](s32)
186 ; MIPS32: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s32), [[MV]], [[MV1]]
224 ; MIPS32: $f0 = COPY [[SELECT]](s32)
[all …]
H A Dfptosi_and_fptoui.mir349 ; FP32: $v0 = COPY [[SELECT]](s32)
364 ; FP64: $v0 = COPY [[SELECT]](s32)
394 ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
411 ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
443 ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
460 ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
531 ; FP32: $v0 = COPY [[SELECT]](s32)
546 ; FP64: $v0 = COPY [[SELECT]](s32)
576 ; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
593 ; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SELECT]], [[C3]]
[all …]
H A Dicmp.mir210 ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
211 ; MIPS32: $v0 = COPY [[SELECT]](s32)
244 ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
245 ; MIPS32: $v0 = COPY [[SELECT]](s32)
278 ; MIPS32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
279 ; MIPS32: $v0 = COPY [[SELECT]](s32)
313 ; MIPS32: $v0 = COPY [[SELECT]](s32)
347 ; MIPS32: $v0 = COPY [[SELECT]](s32)
381 ; MIPS32: $v0 = COPY [[SELECT]](s32)
415 ; MIPS32: $v0 = COPY [[SELECT]](s32)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dselect.mir31 ; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
32 ; MIPS32: $v0 = COPY [[SELECT]](s32)
62 ; MIPS32: [[SELECT:%[0-9]+]]:gprb(p0) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]
63 ; MIPS32: $v0 = COPY [[SELECT]](p0)
100 ; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[LOAD]]
102 ; MIPS32: $v0 = COPY [[SELECT]](s32)
144 ; MIPS32: [[SELECT:%[0-9]+]]:fprb(s64) = G_SELECT [[AND]](s32), [[LOAD]], [[LOAD1]]
145 ; MIPS32: G_STORE [[SELECT]](s64), [[COPY3]](p0) :: (store (s64) into %ir.i64_ptr_c)
181 ; MIPS32: $f0 = COPY [[SELECT]](s32)
214 ; MIPS32: [[SELECT:%[0-9]+]]:gprb(s32) = G_SELECT [[AND]](s32), [[LOAD]], [[LOAD1]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dfloating-point-arithmetic.ll232 ; CHECK-NEXT: ret float [[SELECT]]
244 ; CHECK-NEXT: ret <2 x float> [[SELECT]]
256 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
282 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
308 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
334 ; CHECK-NEXT: ret float [[SELECT]]
346 ; CHECK-NEXT: ret <2 x float> [[SELECT]]
358 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
384 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
410 ; CHECK-NEXT: [[FABS:%.*]] = call float @llvm.fabs.f32(float [[SELECT]])
[all …]

12345678