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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsdwa-preserve.mir4 # SDWA-LABEL: {{^}}add_f16_u32_preserve
6 # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
7 # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
12 # SDWA: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], [[RES]]
59 # SDWA-LABEL: sdwa_preserve_keep
60 # SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
61 # SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
63 # SDWA: v_and_b32_e32 [[AND:v[0-9]+]], 0xff, [[FIRST]]
66 # SDWA: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], [[AND]]
103 # SDWA-LABEL: sdwa_preserve_remove
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H A Dbfe-combine.ll2 ; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN --check-prefix=VI-SDWA %s
8 ; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 2
9 ; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unuse…
13 ; VI-SDWA: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
29 ; VI-SDWA: v_mov_b32_e32 v[[SHIFT:[0-9]+]], 15
30 ; VI-SDWA: v_lshlrev_b32_sdwa v[[ADDRBASE1:[0-9]+]], v[[SHIFT]], v{{[0-9]+}} dst_sel:DWORD dst_unus…
31 ; VI-SDWA: v_lshlrev_b64 v[[[ADDRBASE:[0-9]+]]:{{[^\]+}}], 2, v[[[ADDRBASE1]]:{{[^\]+}}]
32 ; VI-SDWA: v_add_u32_e32 v[[ADDRLO:[0-9]+]], vcc, s{{[0-9]+}}, v[[ADDRBASE]]
H A Dimmv216.ll125 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
150 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
175 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
200 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
226 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
251 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
276 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
301 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
326 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
397 ; FIXME: Shouldn't need right shift and SDWA, also extra copy
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H A Dsdwa-peephole.ll2 …phole -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,GFX89,SDWA,GCN %s
3 …e -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9_10,SDWA,GCN %s
45 ; SDWA: v_mul_u32_u24_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PA…
65 ; SDWA-NOT: v_mul_u32_u24_sdwa
176 ; SDWA: v_mul_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
177 ; SDWA-NOT: v_mul_f16_sdwa
272 ; SDWA-NOT: v_mul_u32_u24_sdwa
400 ; SDWA-DAG: v_cvt_f16_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}
401 ; SDWA-DAG: v_cvt_f16_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}} dst_sel:{{(WORD_1|DWORD)?}} dst_unused:UNUS…
511 ; Check that "pulling out" SDWA operands works correctly.
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H A Dsdwa-stack.mir3 # Do not fold stack objects into SDWA.
H A Dlo16-lo16-physreg-copy-sgpr.mir4 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
H A Dlo16-hi16-illegal-copy.mir6 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
H A Dllc-pipeline.ll587 ; GCN-O1-OPTS-NEXT: SI Peephole SDWA
878 ; GCN-O2-NEXT: SI Peephole SDWA
1183 ; GCN-O3-NEXT: SI Peephole SDWA
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp112 using namespace AMDGPU::SDWA;
367 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
374 if (DstSel == AMDGPU::SDWA::SdwaSel::WORD_1 && in convertToSDWA()
375 getSrcSel() == AMDGPU::SDWA::SdwaSel::WORD_0) { in convertToSDWA()
439 getDstSel() != AMDGPU::SDWA::DWORD) { in convertToSDWA()
1077 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1087 SDWAInst.addImm(AMDGPU::SDWA::DstUnused::UNUSED_PAD); in convertToSDWA()
1097 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1107 SDWAInst.addImm(AMDGPU::SDWA::SdwaSel::DWORD); in convertToSDWA()
1114 DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) { in convertToSDWA()
H A DVOPInstructions.td454 def SDWA {
492 // GFX9 adds two features to SDWA:
493 // 1. Add 3 fields to the SDWA microcode word: S0, S1 and OMOD.
505 // gfx9 SDWA basic encoding
525 // gfx9 SDWA-A
538 // gfx9 SDWA-B
565 let SDWA = 1;
576 let DecoderNamespace = "SDWA";
583 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
586 let SDWA = 1;
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H A DSIDefines.h49 SDWA = 1 << 14, enumerator
268 SDWA = 2, enumerator
763 namespace SDWA {
H A DAMDGPU.td409 "Support SDWA (Sub-DWORD Addressing) extension"
415 "Support OMod with SDWA (Sub-DWORD Addressing) extension"
421 "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
427 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
433 "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
439 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
1309 string SDWA = "SDWA";
1333 let Name = AMDGPUAsmVariants.SDWA;
H A DSIInstrFormats.td34 field bit SDWA = 0;
170 let TSFlags{14} = SDWA;
237 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
H A DSIInstrInfo.td26 int SDWA = 2;
1602 // instructions with SDWA extension
1997 // Ins for SDWA
2050 // Outs for SDWA
2297 0, // NumSrcArgs == 3 - No SDWA for VOP3
2329 // Function that checks if instruction supports DPP and SDWA
2764 // Maps ordinary instructions to their SDWA counterparts
2770 let ValueCols = [["SDWA"]];
2773 // Maps SDWA instructions to their ordinary counterparts
2778 let KeyCol = ["SDWA"];
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H A DAMDGPUInstructionSelector.cpp1976 .addImm(AMDGPU::SDWA::WORD_1) // $dst_sel in selectG_TRUNC()
1977 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused in selectG_TRUNC()
1978 .addImm(AMDGPU::SDWA::WORD_0) // $src0_sel in selectG_TRUNC()
2941 .addImm(AMDGPU::SDWA::WORD_1) // $dst_sel in selectG_SHUFFLE_VECTOR()
2942 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused in selectG_SHUFFLE_VECTOR()
2943 .addImm(AMDGPU::SDWA::WORD_0) // $src0_sel in selectG_SHUFFLE_VECTOR()
2970 .addImm(AMDGPU::SDWA::WORD_0) // $dst_sel in selectG_SHUFFLE_VECTOR()
2971 .addImm(AMDGPU::SDWA::UNUSED_PRESERVE) // $dst_unused in selectG_SHUFFLE_VECTOR()
2972 .addImm(AMDGPU::SDWA::WORD_1) // $src0_sel in selectG_SHUFFLE_VECTOR()
H A DSIInstrInfo.h448 return MI.getDesc().TSFlags & SIInstrFlags::SDWA; in isSDWA()
452 return get(Opcode).TSFlags & SIInstrFlags::SDWA; in isSDWA()
H A DSIInstrInfo.cpp915 .addImm(DstLow ? AMDGPU::SDWA::SdwaSel::WORD_0 in copyPhysReg()
916 : AMDGPU::SDWA::SdwaSel::WORD_1) in copyPhysReg()
917 .addImm(AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) in copyPhysReg()
918 .addImm(SrcLow ? AMDGPU::SDWA::SdwaSel::WORD_0 in copyPhysReg()
919 : AMDGPU::SDWA::SdwaSel::WORD_1) in copyPhysReg()
4200 DstUnused->getImm() == AMDGPU::SDWA::UNUSED_PRESERVE) { in verifyInstruction()
7862 SDWA = 2, enumerator
7924 if (get(Opcode).TSFlags & SIInstrFlags::SDWA) { in pseudoToMCOpcode()
7927 Gen = SIEncodingFamily::SDWA; in pseudoToMCOpcode()
H A DVOP1Instructions.td114 // We only want to set this on the basic, non-SDWA or DPP forms.
544 (inst_sdwa 0, $src, 0, 0, SDWA.WORD_1),
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUInstructionSyntax.rst145 they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
156 *SDWA* encoding _sdwa
H A DAMDGPUInstructionNotation.rst97 :ref:`SDWA operand modifiers<amdgpu_synid_sdwa_operand_modifiers>`.
H A DAMDGPUModifierSyntax.rst1417 SDWA Modifiers
1510 SDWA Operand Modifiers
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp441 using namespace AMDGPU::SDWA; in getSDWASrcEncoding()
472 using namespace AMDGPU::SDWA; in getSDWAVopcDstEncoding()
H A DAMDGPUInstPrinter.cpp377 else if (Flags & SIInstrFlags::SDWA) in printVOPDst()
1026 using namespace llvm::AMDGPU::SDWA; in printSDWASel()
1065 using namespace llvm::AMDGPU::SDWA; in printSDWADstUnused()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3231 (isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) ) in checkTargetMatchPredicate()
3245 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()
3256 AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9, in getAllVariants()
3280 static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA, in getMatchedVariants()
3429 SIInstrFlags::SDWA)) { in validateConstantBusLimitations()
3730 if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc)) in validateMovrels()
4012 const auto Enc = VOP1 | VOP2 | VOP3 | VOPC | VOP3P | SIInstrFlags::SDWA; in validateLdsDirect()
4026 if (IsRevOpcode(Opcode) || (Desc.TSFlags & SIInstrFlags::SDWA)) in validateLdsDirect()
8920 using namespace llvm::AMDGPU::SDWA; in parseSDWASel()
8954 using namespace llvm::AMDGPU::SDWA; in parseSDWADstUnused()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1647 using namespace AMDGPU::SDWA; in decodeSDWASrc()
1695 using namespace AMDGPU::SDWA; in decodeSDWAVopcDst()

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