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Searched refs:SDIV (Results 1 – 25 of 77) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsdiv-canonicalize.ll11 ; CHECK-NEXT: [[SDIV:%.*]] = sub nsw i32 0, [[SDIV1]]
12 ; CHECK-NEXT: ret i32 [[SDIV]]
22 ; CHECK-NEXT: [[SDIV:%.*]] = sub nsw i32 0, [[SDIV1]]
23 ; CHECK-NEXT: ret i32 [[SDIV]]
35 ; CHECK-NEXT: [[SDIV:%.*]] = sdiv i32 [[Y]], [[NEG]]
36 ; CHECK-NEXT: ret i32 [[SDIV]]
47 ; CHECK-NEXT: [[SDIV:%.*]] = sdiv i32 [[NEG]], [[Y:%.*]]
48 ; CHECK-NEXT: ret i32 [[SDIV]]
59 ; CHECK-NEXT: ret <2 x i32> [[SDIV]]
69 ; CHECK-NEXT: [[SDIV:%.*]] = sdiv i32 [[NEG]], [[Y:%.*]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dx86_64-legalize-sdiv.mir50 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]
51 ; CHECK: $al = COPY [[SDIV]](s8)
82 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]
83 ; CHECK: $ax = COPY [[SDIV]](s16)
110 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]]
111 ; CHECK: $eax = COPY [[SDIV]](s32)
136 ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]]
137 ; CHECK: $rax = COPY [[SDIV]](s64)
H A Dx86-legalize-sdiv.mir45 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]
46 ; CHECK: $al = COPY [[SDIV]](s8)
77 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]
78 ; CHECK: $ax = COPY [[SDIV]](s16)
105 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]]
106 ; CHECK: $eax = COPY [[SDIV]](s32)
H A Dx86_64-irtranslator.ll141 ; CHECK: [[SDIV:%[0-9]+]]:_(s8) = G_SDIV [[TRUNC]], [[TRUNC1]]
142 ; CHECK: $al = COPY [[SDIV]](s8)
156 ; CHECK: [[SDIV:%[0-9]+]]:_(s16) = G_SDIV [[TRUNC]], [[TRUNC1]]
157 ; CHECK: $ax = COPY [[SDIV]](s16)
169 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[COPY1]]
170 ; CHECK: $eax = COPY [[SDIV]](s32)
182 ; CHECK: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[COPY]], [[COPY1]]
183 ; CHECK: $rax = COPY [[SDIV]](s64)
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcortex-a57-misched-basic.ll6 ; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).
17 ; GENERIC: SDIV
22 ; A57_SCHED: SDIV
35 ; GENERIC: SDIV
36 ; A57_SCHED: SDIV
H A Dcortexr52-misched-basic.ll17 ; CHECK: SDIV
22 ; GENERIC: SDIV
23 ; R52_SCHED: SDIV
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-divrem.mir31 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
32 ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
34 ; CHECK: $w0 = COPY [[SDIV]](s32)
56 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
58 ; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[COPY2]]
61 ; CHECK: $w0 = COPY [[SDIV]](s32)
H A Dlegalize-div.mir14 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
15 ; CHECK: $w0 = COPY [[SDIV]](s32)
50 ; CHECK: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[UV]], [[UV4]]
54 …; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SDIV]](s32), [[SDIV1]](s32), [[S…
H A Dlegalize-rem.mir29 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[TRUNC]], [[TRUNC1]]
30 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
52 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
54 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC2]]
78 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[SEXT_INREG]], [[SEXT_INREG1]]
79 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[SEXT_INREG1]]
160 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[UV]], [[UV2]]
162 … ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SDIV]](s32), [[SDIV1]](s32)
204 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s64) = G_SDIV [[UV]], [[UV2]]
207 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[SDIV]], [[UV4]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Drem_and_div.mir24 ; MIPS32: [[SDIV:%[0-9]+]]:gprb(s32) = G_SDIV [[COPY1]], [[COPY]]
25 ; MIPS32: $v0 = COPY [[SDIV]](s32)
H A Drem_and_div_vec.mir42 ; P5600: [[SDIV:%[0-9]+]]:fprb(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
43 ; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
71 ; P5600: [[SDIV:%[0-9]+]]:fprb(<8 x s16>) = G_SDIV [[LOAD]], [[LOAD1]]
72 ; P5600: G_STORE [[SDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
100 ; P5600: [[SDIV:%[0-9]+]]:fprb(<4 x s32>) = G_SDIV [[LOAD]], [[LOAD1]]
101 ; P5600: G_STORE [[SDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
129 ; P5600: [[SDIV:%[0-9]+]]:fprb(<2 x s64>) = G_SDIV [[LOAD]], [[LOAD1]]
130 ; P5600: G_STORE [[SDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dgep.ll13 ; CHECK-NEXT: [[SDIV:%.*]] = sdiv exact i64 [[SUB]], 7
14 ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [[STRUCT_A:%.*]], ptr [[B]], i64 [[SDIV]]
64 ; CHECK-NEXT: [[SDIV:%.*]] = sdiv exact i64 [[SUB]], 7
65 ; CHECK-NEXT: [[GEP:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[B]], i64 [[SDIV]]
79 ; CHECK-NEXT: [[SDIV:%.*]] = sdiv exact i64 [[SUB]], 7
80 ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds [[STRUCT_A:%.*]], ptr [[B]], i64 [[SDIV]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Drem_and_div_vec.mir41 ; P5600: [[SDIV:%[0-9]+]]:_(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
42 ; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
69 ; P5600: [[SDIV:%[0-9]+]]:_(<8 x s16>) = G_SDIV [[LOAD]], [[LOAD1]]
70 ; P5600: G_STORE [[SDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
97 ; P5600: [[SDIV:%[0-9]+]]:_(<4 x s32>) = G_SDIV [[LOAD]], [[LOAD1]]
98 ; P5600: G_STORE [[SDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
125 ; P5600: [[SDIV:%[0-9]+]]:_(<2 x s64>) = G_SDIV [[LOAD]], [[LOAD1]]
126 ; P5600: G_STORE [[SDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Drem_and_div_vec_builtin.mir69 ; P5600: [[SDIV:%[0-9]+]]:_(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
70 ; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
97 ; P5600: [[SDIV:%[0-9]+]]:_(<8 x s16>) = G_SDIV [[LOAD]], [[LOAD1]]
98 ; P5600: G_STORE [[SDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
125 ; P5600: [[SDIV:%[0-9]+]]:_(<4 x s32>) = G_SDIV [[LOAD]], [[LOAD1]]
126 ; P5600: G_STORE [[SDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
153 ; P5600: [[SDIV:%[0-9]+]]:_(<2 x s64>) = G_SDIV [[LOAD]], [[LOAD1]]
154 ; P5600: G_STORE [[SDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
H A Drem_and_div.mir40 ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
41 ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SDIV]], [[C]](s32)
72 ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[ASHR]], [[ASHR1]]
73 ; MIPS32: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[SDIV]], [[C]](s32)
99 ; MIPS32: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY1]], [[COPY]]
100 ; MIPS32: $v0 = COPY [[SDIV]](s32)
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp340 case ISD::SDIV: in Select()
351 if (N->getOpcode() == ISD::SDIV) { in Select()
363 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; in Select()
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/ARM/
H A Dsigned.ll38 ; CHECK-NEXT: [[SDIV:%.*]] = sdiv i16 [[ARG:%.*]], 2
39 ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i16 [[SDIV]], 0
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h109 case ISD::SDIV:
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1341 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1345 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1349 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost}, in getArithmeticInstrCost()
1353 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost}, in getArithmeticInstrCost()
1358 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1362 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1366 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1370 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
1925 case ISD::SDIV: in maybeLoweredToCall()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def100 ADD_BINARY_VVP_OP_COMPACT(SDIV)
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp253 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
379 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
399 { ISD::SDIV, MVT::v8i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
423 { ISD::SDIV, MVT::v4i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
444 { ISD::SDIV, MVT::v32i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
459 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
467 { ISD::SDIV, MVT::v32i16, 12 }, // 2*vpmulhw sequence in getArithmeticInstrCost()
486 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
490 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
514 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence in getArithmeticInstrCost()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h242 SDIV, enumerator
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-expand-div.ll7 ; SDIV
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1922 case ISD::SDIV: in selectDivRem()
1924 DivOpc = Mips::SDIV; in selectDivRem()
2037 if (!selectBinaryOp(I, ISD::SDIV)) in fastSelectInstruction()
2038 return selectDivRem(I, ISD::SDIV); in fastSelectInstruction()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp190 case ISD::SDIV: { in Select()

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