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/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dctlz.ll14 ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
15 ; CHECK: lsr {{.*}}[[SCRATCH]]
16 ; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
17 ; CHECK: mov {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
20 ; CHECK: or {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
22 ; CHECK: swap {{.*}}[[SCRATCH]]
23 ; CHECK: andi {{.*}}[[SCRATCH]], 15
25 ; CHECK: com {{.*}}[[SCRATCH]]
32 ; CHECK: lsr {{.*}}[[SCRATCH]]
33 ; CHECK: lsr {{.*}}[[SCRATCH]]
[all …]
H A Dcttz.ll14 ; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
15 ; CHECK: dec {{.*}}[[SCRATCH]]
17 ; CHECK: and {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
18 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
19 ; CHECK: lsr {{.*}}[[SCRATCH]]
20 ; CHECK: andi {{.*}}[[SCRATCH]], 85
21 ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
23 ; CHECK: andi {{.*}}[[SCRATCH]], 51
29 ; CHECK: swap {{.*}}[[SCRATCH]]
31 ; CHECK: andi {{.*}}[[SCRATCH]], 15
[all …]
H A Dctpop.ll12 ; CHECK: mov [[SCRATCH:r[0-9]+]], [[RESULT:r[0-9]+]]
13 ; CHECK: lsr {{.*}}[[SCRATCH]]
14 ; CHECK: andi {{.*}}[[SCRATCH]], 85
15 ; CHECK: sub {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
16 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
17 ; CHECK: andi {{.*}}[[SCRATCH]], 51
21 ; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
22 ; CHECK: mov {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]
23 ; CHECK: swap {{.*}}[[SCRATCH]]
24 ; CHECK: add {{.*}}[[RESULT]], {{.*}}[[SCRATCH]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dgfx-callable-argument-types.ll184 ; GFX10-SCRATCH: ; %bb.0:
309 ; GFX10-SCRATCH: ; %bb.0:
437 ; GFX10-SCRATCH: ; %bb.0:
557 ; GFX10-SCRATCH: ; %bb.0:
676 ; GFX10-SCRATCH: ; %bb.0:
797 ; GFX10-SCRATCH: ; %bb.0:
915 ; GFX10-SCRATCH: ; %bb.0:
1034 ; GFX10-SCRATCH: ; %bb.0:
1155 ; GFX10-SCRATCH: ; %bb.0:
1273 ; GFX10-SCRATCH: ; %bb.0:
[all …]
H A Dmemory_clause.ll26 ; GCN-SCRATCH-LABEL: vector_clause:
27 ; GCN-SCRATCH: ; %bb.0: ; %bb
32 ; GCN-SCRATCH-NEXT: s_clause 0x3
45 ; GCN-SCRATCH-NEXT: s_endpgm
102 ; GCN-SCRATCH-LABEL: scalar_clause:
131 ; GCN-SCRATCH-NEXT: s_endpgm
291 ; GCN-SCRATCH-NEXT: s_endpgm
439 ; GCN-SCRATCH-NEXT: ;;#ASMEND
450 ; GCN-SCRATCH-NEXT: s_endpgm
502 ; GCN-SCRATCH-NEXT: ;;#ASMEND
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dtoc-data.ll63 ; CHECK64: LD 0, killed %[[SCRATCH]]
67 ; CHECK64-NOOPT: LD 0, %[[SCRATCH]]
93 ; CHECK64-NOOPT: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]]
114 ; CHECK64: STFD %{{[0-9]+}}, 0, killed %[[SCRATCH]]
118 ; CHECK64-NOOPT STFD %{{[0-9]+}}, 0 %[[SCRATCH]]
130 ; CHECK32: %[[SCRATCH:[0-9]+]]:gprc = ADDItoc @i, $r2
131 ; CHECK32-NEXT: $r3 = COPY %[[SCRATCH]]
137 ; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc = ADDItoc8 @i, $x2
138 ; CHECK64-NEXT: $x3 = COPY %[[SCRATCH]]
141 ; CHECK64-NOOPT: %[[SCRATCH:[0-9]+]]:g8rc = ADDItoc8 @i, $x2
[all …]
H A Daix-vector-stack.ll14 ; 32BIT: addi [[SCRATCH:[0-9]+]], 1, 48
15 ; 32BIT-NEXT: lxvw4x 34, 0, [[SCRATCH]]
17 ; 64BIT: addi [[SCRATCH:[0-9]+]], 1, 64
18 ; 64BIT-NEXT: lxvw4x 34, 0, [[SCRATCH]]
H A Daix64-cc-byval.ll99 ; CHECK: renamable $x[[SCRATCH:[0-9]+]] = COPY $x3
101 ; CHECK-DAG: STD killed renamable $x[[SCRATCH]], 0, %fixed-stack.0 :: (store (s64) into %fixed…
106 ; ASM: mr [[SCRATCH:[0-9]+]], 3
108 ; ASM-DAG: std [[SCRATCH]], 48(1)
H A Daix-cc-byval.ll421 ; 32BIT-DAG: renamable $r[[SCRATCH:[0-9]+]] = RLWINM killed renamable $r3, 0, 24, 31
422 ; 32BIT-DAG: renamable $r3 = nsw ADD4 renamable $r4, killed renamable $r[[SCRATCH]]
447 ; ASM32-DAG: clrlwi [[SCRATCH:[0-9]+]], 3, 24
448 ; ASM32-DAG: add 3, 4, [[SCRATCH]]
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/pseudo/
H A DLDWRdPtr-same-src-dst.mir22 ; CHECK: ld [[SCRATCH:r[0-9]+]], Z
23 ; CHECK-NEXT: push [[SCRATCH]]
24 ; CHECK-NEXT: ldd [[SCRATCH]], Z+1
25 ; CHECK-NEXT: mov r31, [[SCRATCH]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dframelayout-scavengingslot.mir8 # CHECK: STRXui killed $[[SCRATCH:x[0-9]+]], $sp, 0
9 # CHECK-NEXT: $[[SCRATCH]] = ADDXri $sp, 40, 0
10 # CHECK-NEXT: STRXui $x0, killed $[[SCRATCH]], 4095
11 # CHECK-NEXT: $[[SCRATCH]] = LDRXui $sp, 0
H A Dframelayout-sve-scavengingslot.mir10 # CHECK: STRXui killed $[[SCRATCH:x[0-9]+]], $sp, 0
11 # CHECK-NEXT: $[[SCRATCH]] = ADDVL_XXI $fp, -1
12 # CHECK-NEXT: STRXui $x0, killed $[[SCRATCH]], 0
H A Dframelayout-sve.mir59 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
71 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 16
121 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -32
139 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 32
266 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
286 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 16
427 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
442 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 16
500 # CHECK-NEXT: $sp = frame-setup STRXpre killed $[[SCRATCH:[a-z0-9]+]], $sp, -16
546 # CHECK-NEXT: $sp, $[[SCRATCH]] = frame-destroy LDRXpost $sp, 16
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A D2014-02-21-byval-reg-split-alignment.ll19 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #12
20 ; CHECK: stm [[SCRATCH]], {r1, r2, r3}
54 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8
55 ; CHECK: stm [[SCRATCH]], {r0, r1, r2}
91 ; CHECK: add [[SCRATCH:r[0-9]+]], sp, #8
92 ; CHECK: stm [[SCRATCH]], {r0, r1, r2, r3}
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp72 SCRATCH = 1u << 2, enumerator
77 FLAT = GLOBAL | LDS | SCRATCH,
80 ATOMIC = GLOBAL | LDS | SCRATCH | GDS,
83 ALL = GLOBAL | LDS | SCRATCH | GDS | OTHER,
141 if ((InstrAddrSpace & ~SIAtomicAddrSpace::SCRATCH) == in SIMemOpInfo()
145 ~(SIAtomicAddrSpace::SCRATCH | SIAtomicAddrSpace::LDS)) == in SIMemOpInfo()
149 ~(SIAtomicAddrSpace::SCRATCH | SIAtomicAddrSpace::LDS | in SIMemOpInfo()
678 return SIAtomicAddrSpace::SCRATCH; in toSIAtomicAddrSpace()
981 if ((AddrSpace & (SIAtomicAddrSpace::GLOBAL | SIAtomicAddrSpace::SCRATCH)) != in insertWait()
1330 if (((AddrSpace & (SIAtomicAddrSpace::GLOBAL | SIAtomicAddrSpace::SCRATCH | in insertWait()
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Dmemcpy-from-constant.ll208 …m.memcpy.p0i8.p4i8.i32(i8* noundef nonnull align 4 dereferenceable(16) [[SCRATCH:%.*]], i8 addrspa…
224 …m.memcpy.p0i8.p4i8.i32(i8* noundef nonnull align 4 dereferenceable(16) [[SCRATCH:%.*]], i8 addrspa…
244 …m.memcpy.p0i8.p0i8.i64(i8* noundef nonnull align 4 dereferenceable(16) [[SCRATCH:%.*]], i8* nounde…
261 ….memmove.p0i8.p4i8.i32(i8* noundef nonnull align 4 dereferenceable(16) [[SCRATCH:%.*]], i8 addrspa…
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dflat-gfx11.txt433 # SCRATCH
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUUsage.rst4890 FLAT SCRATCH BASE in flat memory instructions that access the scratch
4905 GFX7 and SGPRn-5 on GFX8. FLAT_SCRATCH_LO is used as the FLAT SCRATCH SIZE
4924 which is SGPRn-6 and SGPRn-5. It is used as the FLAT SCRATCH BASE in flat
4948 Instead the flat SCRATCH instructions are used.
13804 - If ``SCRATCH`` instruction could allow negative offsets, then can make FP be