| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 37 struct S29 { virtual void f(); }; struct 84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | microsoft-abi-static-initializers.cpp | 88 static S S29; in MultipleStatics() local
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| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | swim.c | 32 S29(c0, c1);
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| H A D | swim.st | 1 … i0 <= P and i1 >= 1 and i1 <= R; S70[i0] : M = 1 and i0 >= 2 and i0 <= P; S29[i0, i1] : M = 1 and… 33 - filter: "[M, N, O, P, Q, R] -> { S30[i0, i1]; S28[i0, i1]; S31[i0]; S29[i0, i1] }" 35 …schedule: "[M, N, O, P, Q, R] -> [{ S31[i0] -> [(i0)]; S29[i0, i1] -> [(i0)]; S30[i0, i1] -> [(i0)… 39 - filter: "[M, N, O, P, Q, R] -> { S30[i0, i1]; S28[i0, i1]; S29[i0, i1] }" 41 …schedule: "[M, N, O, P, Q, R] -> [{ S29[i0, i1] -> [(i1)]; S30[i0, i1] -> [(i1)]; S28[i0, i1] -> [… 46 - filter: "[M, N, O, P, Q, R] -> { S29[i0, i1] }"
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 61 case AArch64::S29: in isOdd()
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| H A D | AArch64RegisterInfo.td | 358 def S29 : AArch64Reg<29, "s29", [H29]>, DwarfRegAlias<B29>; 393 def D29 : AArch64Reg<29, "d29", [S29], ["v29", ""]>, DwarfRegAlias<B29>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 116 def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; 135 def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 278 {codeview::RegisterId::ARM_FS29, ARM::S29}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 167 {codeview::RegisterId::ARM64_S29, AArch64::S29}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 126 // CHECK-NEXT: %[[S29:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [2, 0], sizes = [2, 2]… 127 …"parallel", "reduction"], kind = #vector.kind<add>} %[[S27]], %[[S28]], %[[S29]], %[[S30]], %[[S31…
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 280 S23, S24, S25, S26, S27, S28, S29, S30, S31
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| H A D | PPCFrameLowering.cpp | 196 {PPC::S29, -24}, in getCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1500 ARM::S28, ARM::S29, ARM::S30, ARM::S31
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