| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 144 struct S27 { // expected-warning {{padding size of 'S27' with 7 bits to alignment boundary}} struct
153 S26*, S27*){} in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 86 static S S27; in MultipleStatics() local
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| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 35 struct S27 { virtual void f(); }; struct
84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
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| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | swim.c | 28 S27();
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| H A D | swim.st | 1 …0 >= 2 and i0 <= P; S93[i0] : M = 1 and i0 >= 2 and i0 <= P; S2[] : M = 1; S27[] : M = 1; S122[i0]…
32 - filter: "[M, N, O, P, Q, R] -> { S27[] }"
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 60 case AArch64::S27: in isOdd()
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| H A D | AArch64RegisterInfo.td | 356 def S27 : AArch64Reg<27, "s27", [H27]>, DwarfRegAlias<B27>;
391 def D27 : AArch64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias<B27>;
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 1336 MCOperand S27 = Inst.getOperand(1); in processInstruction() local
1337 HexagonMCInstrInfo::setMustNotExtend(*S27.getExpr()); in processInstruction()
1338 HexagonMCInstrInfo::setS27_2_reloc(*S27.getExpr()); in processInstruction()
1342 Inst.addOperand(S27); in processInstruction()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 115 def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
134 def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 276 {codeview::RegisterId::ARM_FS27, ARM::S27}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 165 {codeview::RegisterId::ARM64_S27, AArch64::S27}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 122 // CHECK-NEXT: %[[S27:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [2, 0], sizes = [2, 2]…
127 …ypes = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %[[S27]], %[[S28]], %[[S29…
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 280 S23, S24, S25, S26, S27, S28, S29, S30, S31
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| H A D | PPCFrameLowering.cpp | 198 {PPC::S27, -40}, in getCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1499 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
|