| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 271 S26(10, c1, 3);
294 S26(10, 4, 3);
309 S26(10, 5, 3);
344 S26(c0, c1, 3);
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| H A D | usvd_e_t.st | 1 … and i0 <= 4; S2[i0, i1, 0] : i0 >= 0 and i0 <= 4 and i1 >= 0 and i1 <= 4; S26[i0, i1, 3] : i0 >= …
5 …S26[i0, i1, i2] -> [(i0)]; S5[i0, i1, i2] -> [(i0)]; S2[i0, i1, i2] -> [(i0)]; S4[i0, i1, i2] -> […
34 - filter: "{ S26[i0, i1, i2] }"
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| H A D | swim.c | 27 S26();
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| H A D | swim.st | 1 … : M = 1 and i0 >= 2 and i0 <= P; S85[i0] : M = 1 and i0 >= 2 and i0 <= P; S26[] : M = 1; S79[i0] …
31 - filter: "[M, N, O, P, Q, R] -> { S26[] }"
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 139 struct S26 { // expected-warning {{packed attribute is unnecessary for 'S26'}} struct
153 S26*, S27*){} in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 85 static S S26; in MultipleStatics() local
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| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 34 struct S26 { virtual void f(); }; struct
84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 109 case AArch64::S26: in isOdd()
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| H A D | AArch64RegisterInfo.td | 355 def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>;
390 def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 315 def S26 : Rs<26, "s26">, DwarfRegNum<[170]>;
387 def S27_26 : Rss<26, "s27:26", [S26, CFGBASE]>, DwarfRegNum<[170]>;
603 S26, CFGBASE, DIAG, REV, PCYCLEHI,
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 115 def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
134 def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 275 {codeview::RegisterId::ARM_FS26, ARM::S26}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 164 {codeview::RegisterId::ARM64_S26, AArch64::S26}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 117 // CHECK-NEXT: %[[S26:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
118 …"], kind = #vector.kind<add>} %[[S23]], %[[S24]], %[[R2S02]], %[[S25]], %[[S26]] : vector<2x2xf32>…
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 280 S23, S24, S25, S26, S27, S28, S29, S30, S31
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| H A D | PPCFrameLowering.cpp | 199 {PPC::S26, -48}, in getCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 786 Hexagon::S24, Hexagon::S25, Hexagon::S26,
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1499 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
|