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Searched refs:S25 (Results 1 – 21 of 21) sorted by relevance

/llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/
H A Dusvd_e_t.c274 S25(10, c1, 4);
300 S25(10, 4, 4);
315 S25(10, 5, 4);
345 S25(c0, c1, 4);
H A Dusvd_e_t.st1 … <= -4 + i0; S8[i0, i1, 0] : i0 >= 3 and i0 <= 7 and i1 >= 7 and i1 <= 11; S25[i0, i1, 4] : i0 >= …
5 …S25[i0, i1, i2] -> [(i0)]; S18[i0, i1, i2] -> [(i0)]; S26[i0, i1, i2] -> [(i0)]; S5[i0, i1, i2] ->…
33 - filter: "{ S25[i0, i1, i2] }"
H A Dswim.c26 S25();
H A Dswim.st1 …<= P; S63[i0, i1] : M = 1 and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= Q; S25[] : M = 1; S51[i0, …
30 - filter: "[M, N, O, P, Q, R] -> { S25[] }"
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dwarn-padded-packed.cpp134 struct S25 { // expected-warning {{padding size of 'S25' with 7 bits to alignment boundary}} expect… struct
152 S14*, S15*, S16*, S17*, S18*, S19*, S20*, S21*, S22*, S23*, S24*, S25*, in f() argument
H A Dmicrosoft-abi-static-initializers.cpp84 static S S25; in MultipleStatics() local
/llvm-project-15.0.7/clang/test/PCH/
H A Dcxx-key-functions.cpp33 struct S25 { virtual void f(); }; struct
84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrFormats.td178 bits<25> S25; // 2-byte aligned 25-bit byte-offset.
179 let Inst{26-18} = S25{10-2};
180 let Inst{15-6} = S25{20-11};
182 let Inst{3-0} = S25{24-21};
190 // Branch targets are 2-byte aligned, so S25[0] is implied 0.
192 // |S25[10-1] | 1|S25[20-11] |N|0|S25[24-21]|
195 let Inst{17} = S25{1};
198 // BL targets (functions) are 4-byte aligned, so S25[1-0] = 0b00
200 // |S25[10-2] | 1| 0|S25[20-11] |N|0|S25[24-21]|
208 // |S25[10-2] | 0| 0|S25[20-11] |N|0|cc |
H A DARCInstrInfo.td429 def BR : F32_BR0_UCOND_FAR<(outs), (ins btargetS25:$S25),
430 "b\t$S25", [(br bb:$S25)]>;
479 def BL : F32_BR1_BL_UCOND_FAR<(outs), (ins calltargetS25:$S25),
480 "bl\t$S25", [(ARCBranchLink tglobaladdr:$S25)]>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp59 case AArch64::S25: in isOdd()
H A DAArch64RegisterInfo.td354 def S25 : AArch64Reg<25, "s25", [H25]>, DwarfRegAlias<B25>;
389 def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td314 def S25 : Rs<25, "s25">, DwarfRegNum<[169]>;
386 def S25_24 : Rss<24, "s25:24", [S24, S25]>, DwarfRegNum<[168]>;
601 S19, S23, S25,
/llvm-project-15.0.7/clang/test/Modules/
H A Dodr_hash.cpp3165 struct S25 { struct
3169 struct S25 { struct
3174 S25 s25;
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td114 def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
133 def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp274 {codeview::RegisterId::ARM_FS25, ARM::S25}, in initLLVMToCVRegMapping()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp163 {codeview::RegisterId::ARM64_S25, AArch64::S25}, in initLLVMToCVRegMapping()
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transforms.mlir115 // CHECK-NEXT: %[[S25:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
118 …"reduction"], kind = #vector.kind<add>} %[[S23]], %[[S24]], %[[R2S02]], %[[S25]], %[[S26]] : vecto…
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td280 S23, S24, S25, S26, S27, S28, S29, S30, S31
H A DPPCFrameLowering.cpp200 {PPC::S25, -56}, in getCalleeSavedSpillSlots()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp786 Hexagon::S24, Hexagon::S25, Hexagon::S26,
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1499 ARM::S24, ARM::S25, ARM::S26, ARM::S27,