| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 49 S23(7, 4, 0);
58 S23(7, 5, 0);
66 S23(7, 6, 0);
127 S23(8, 4, 0);
130 S23(8, 4, 1);
140 S23(8, 5, 0);
144 S23(8, 5, 1);
154 S23(8, 6, 0);
158 S23(8, 6, 1);
212 S23(9, 4, 2);
[all …]
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| H A D | usvd_e_t.st | 1 …S12[i0, -2 + i0, i2] : i0 >= 7 and i0 <= 10 and i2 <= 4 and i2 >= -7 + i0; S23[i0, i1, i2] : i0 <=…
5 …S23[i0, i1, i2] -> [(i0)]; S22[i0, i1, i2] -> [(i0)]; S16[i0, i1, i2] -> [(i0)]; S17[i0, i1, i2] -…
31 - filter: "{ S23[i0, i1, i2] }"
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| H A D | swim.c | 24 S23();
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| H A D | swim.st | 1 …= P; S109[i0, i1] : M = 1 and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= Q; S23[] : M = 1; S82[i0] …
28 - filter: "[M, N, O, P, Q, R] -> { S23[] }"
|
| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 118 struct S23 { // expected-warning {{padding size of 'S23' with 4 bits to alignment boundary}} expect… struct
152 S14*, S15*, S16*, S17*, S18*, S19*, S20*, S21*, S22*, S23*, S24*, S25*, in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 82 static S S23; in MultipleStatics() local
|
| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 31 struct S23 { virtual void f(); }; struct
84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | 2012-02-14-scalar.ll | 11 %S23 = select i1 %E19, i8 undef, i8 undef
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | no-register-coalescing-in-returnsTwice.mir | 31 …%struct.S18 = type <{ i32, [4 x i8], double, double, double, i32, [4 x i8], %struct.S23, i32, [4 x…
32 %struct.S23 = type { [2 x double], half }
65 %8 = bitcast %struct.S23* %M3.i to i8*
|
| /llvm-project-15.0.7/llvm/unittests/Support/ |
| H A D | HashBuilderTest.cpp | 254 llvm::StringRef S23("23"); in TYPED_TEST() local
259 auto Hash1And23 = hashWithBuilder<HE>(S1, S23); in TYPED_TEST()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 58 case AArch64::S23: in isOdd()
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| H A D | AArch64RegisterInfo.td | 352 def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>;
387 def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>;
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 312 def S23 : Rs<23, "s23">, DwarfRegNum<[167]>;
385 def S23_22 : Rss<22, "s23:22", [S22, S23]>, DwarfRegNum<[166]>;
601 S19, S23, S25,
|
| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 3129 struct S23 { struct
3135 struct S23 { struct
3141 S23 s23;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 113 def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
132 def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>;
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| H A D | ARMCallingConv.td | 116 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 272 {codeview::RegisterId::ARM_FS23, ARM::S23}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 161 {codeview::RegisterId::ARM64_S23, AArch64::S23}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 114 // CHECK-NEXT: %[[S23:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [0, 4], sizes = [2, 2]…
118 …ypes = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %[[S23]], %[[S24]], %[[R2S…
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 280 S23, S24, S25, S26, S27, S28, S29, S30, S31
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| H A D | PPCFrameLowering.cpp | 202 {PPC::S23, -72}, in getCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 785 Hexagon::VID, Hexagon::S22, Hexagon::S23,
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1498 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
|