| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 94 S20(8, 2, -2);
98 S20(8, 2, -1);
101 S20(8, 2, 0);
110 S20(8, 3, -1);
112 S20(8, 3, 0);
121 S20(8, 4, -1);
126 S20(8, 4, 0);
185 S20(9, 3, -4);
199 S20(9, 4, -4);
207 S20(9, 4, 0);
[all …]
|
| H A D | usvd_e_t.st | 1 …2] : i0 <= 10 and i1 >= 4 and i2 <= 4 and i2 >= -7 + i0 and i1 <= -4 + i0; S20[i0, i1, i2] : i0 >=…
5 …S20[i0, i1, i2] -> [(i0)]; S11[i0, i1, i2] -> [(i0)]; S1[i0, i1, i2] -> [(i0)] }, { S8[i0, i1, i2]…
28 - filter: "{ S20[i0, i1, i2] }"
|
| H A D | swim.c | 21 S20();
|
| H A D | swim.st | 1 … = 1; S28[i0, i1] : M = 1 and i0 >= 1 and i0 <= N and i1 >= 1 and i1 <= N; S20[] : M = 1; S117[i0,…
25 - filter: "[M, N, O, P, Q, R] -> { S20[] }"
|
| /llvm-project-15.0.7/compiler-rt/test/asan/TestCases/Linux/ |
| H A D | sized_delete_test.cpp | 21 struct S20 { struct
63 Del12Ar(reinterpret_cast<S12*>(new S20[100])); in main()
64 Del12NoThrow(reinterpret_cast<S12*>(new S20)); in main()
65 Del12ArNoThrow(reinterpret_cast<S12*>(new S20[100])); in main()
72 Del12(reinterpret_cast<S12*>(new S20)); in main()
|
| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | attr-trivial-abi.cpp | 163 struct __attribute__((trivial_abi)) S20 { struct
167 static_assert(!__is_trivially_relocatable(S20), "");
169 static_assert(__is_trivially_relocatable(S20), "");
|
| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 103 struct S20 { struct
152 S14*, S15*, S16*, S17*, S18*, S19*, S20*, S21*, S22*, S23*, S24*, S25*, in f() argument
|
| H A D | microsoft-abi-static-initializers.cpp | 79 static S S20; in MultipleStatics() local
|
| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 28 struct S20 { virtual void f(); }; struct
84 S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
|
| /llvm-project-15.0.7/clang/test/SemaObjCXX/ |
| H A D | attr-trivial-abi.mm | 131 struct __attribute__((trivial_abi)) S20 {
|
| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 110 // CHECK-NEXT: %[[S20:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [2, 2], sizes = [2, 2]…
112 …arallel", "parallel", "reduction"], kind = #vector.kind<add>} %[[S19]], %[[S20]], %[[R1S02]], %[[S…
224 // CHECK-NEXT: %[[S20:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
226 …el"], kind = #vector.kind<add>} %[[S16]], %[[S17]], %[[S18]], %[[S19]], %[[S20]] : vector<2x2xf32>…
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 106 case AArch64::S20: in isOdd()
|
| H A D | AArch64RegisterInfo.td | 349 def S20 : AArch64Reg<20, "s20", [H20]>, DwarfRegAlias<B20>;
384 def D20 : AArch64Reg<20, "d20", [S20], ["v20", ""]>, DwarfRegAlias<B20>;
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 309 def S20 : Rs<20, "s20", ["s20"]>, DwarfRegNum<[164]>;
384 def S21_20 : Rss<20, "s21:20", [S20, VID]>, DwarfRegNum<[164]>;
602 EVB, MODECTL, SYSCFG, S20, VID, S22, S24,
|
| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 3079 struct S20 { struct
3084 struct S20 { struct
3089 S20 s20;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 112 def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
131 def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
|
| H A D | ARMCallingConv.td | 116 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 269 {codeview::RegisterId::ARM_FS20, ARM::S20}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 158 {codeview::RegisterId::ARM64_S20, AArch64::S20}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 279 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
|
| H A D | PPCFrameLowering.cpp | 205 {PPC::S20, -96}, in getCalleeSavedSpillSlots()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 784 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
|
| /llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/AArch64/ |
| H A D | select-shuffle.ll | 232 ; CHECK-NEXT: [[S20:%.*]] = shufflevector <16 x i32> [[Y]], <16 x i32> [[X]], <16 x i32> <i32 29…
233 ; CHECK-NEXT: [[A0:%.*]] = add nsw <16 x i32> [[S10]], [[S20]]
234 ; CHECK-NEXT: [[B0:%.*]] = sub nsw <16 x i32> [[S10]], [[S20]]
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1498 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
|