| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 87 S18(8, 1, 4);
103 S18(8, 2, 4);
114 S18(8, 3, 4);
182 S18(9, c1, c2);
197 S18(9, 3, c2);
221 S18(9, 4, c2);
273 S18(10, c1, 4);
299 S18(10, 4, 4);
303 S18(10, 4, c2);
314 S18(10, 5, 4);
[all …]
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| H A D | usvd_e_t.st | 1 …; S3[i0, 0, 0] : i0 >= 4 and i0 <= 8; S9[i0, 4, 0] : i0 >= 7 and i0 <= 10; S18[i0, i1, i2] : i0 <=…
5 …S18[i0, i1, i2] -> [(i0)]; S26[i0, i1, i2] -> [(i0)]; S5[i0, i1, i2] -> [(i0)]; S2[i0, i1, i2] -> …
26 - filter: "{ S18[i0, i1, i2] }"
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| H A D | swim.c | 19 S18();
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| H A D | swim.st | 1 …1 and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= Q and i2 >= 1 and i2 <= R; S18[] : M = 1; S48[i0, …
23 - filter: "[M, N, O, P, Q, R] -> { S18[] }"
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | no-register-coalescing-in-returnsTwice.mir | 31 …%struct.S18 = type <{ i32, [4 x i8], double, double, double, i32, [4 x i8], %struct.S23, i32, [4 x…
36 %0 = bitcast %struct.S37* %P0 to %struct.S18*
38 %P1 = alloca %struct.S18, align 8
59 %7 = bitcast %struct.S18* %0 to i8*
60 %BM0.i = getelementptr inbounds %struct.S18, %struct.S18* %0, i32 0, i32 2
62 %M0.i = getelementptr inbounds %struct.S18, %struct.S18* %0, i32 0, i32 5
64 %M3.i = getelementptr inbounds %struct.S18, %struct.S18* %0, i32 0, i32 7
74 …call void (i64*, %struct.S18*, ...) @_Z3fooPx3S18z(i64* nonnull %10, %struct.S18* nonnull byval(%s…
78 %12 = bitcast %struct.S18* %0 to i8*
83 declare void @_Z3fooPx3S18z(i64*, %struct.S18* byval(%struct.S18) align 8, ...)
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| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | attr-trivial-abi.cpp | 127 struct __attribute__((trivial_abi)) S18 { // expected-warning {{'trivial_abi' cannot be applied to … struct
131 static_assert(__is_trivially_relocatable(S18), "");
133 static_assert(!__is_trivially_relocatable(S18), "");
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| /llvm-project-15.0.7/clang/test/SemaObjCXX/ |
| H A D | attr-trivial-abi.mm | 99 struct __attribute__((trivial_abi)) S18 { // expected-warning {{'trivial_abi' cannot be applied to …
111 …struct __attribute__((trivial_abi)) S18 { // expected-warning {{'trivial_abi' cannot be applied to…
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 93 struct S18 { // expected-warning {{padding size of 'S18' with 2 bytes to alignment boundary}} expec… struct
152 S14*, S15*, S16*, S17*, S18*, S19*, S20*, S21*, S22*, S23*, S24*, S25*, in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 77 static S S18; in MultipleStatics() local
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| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 26 struct S18 { virtual void f(); }; struct
83 S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
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| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 104 // CHECK-NEXT: %[[S18:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
106 …on"], kind = #vector.kind<add>} %[[S14]], %[[S15]], %[[S16]], %[[S17]], %[[S18]] : vector<2x2xf32>…
225 // CHECK-NEXT: %[[S18:.*]] = vector.extract_strided_slice %arg2 {offsets = [2, 2], sizes = [2, 2], …
226 …"reduction", "parallel"], kind = #vector.kind<add>} %[[S16]], %[[S17]], %[[S18]], %[[S19]], %[[S20…
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 105 case AArch64::S18: in isOdd()
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| H A D | AArch64RegisterInfo.td | 347 def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>;
382 def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
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| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 3047 struct S18 { struct
3052 struct S18 { struct
3057 S18 s18;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 111 def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
130 def D9 : ARMReg< 9, "d9", [S18, S19]>, DwarfRegNum<[265]>;
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| H A D | ARMCallingConv.td | 116 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 267 {codeview::RegisterId::ARM_FS18, ARM::S18}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 156 {codeview::RegisterId::ARM64_S18, AArch64::S18}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 279 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
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| H A D | PPCFrameLowering.cpp | 207 {PPC::S18, -112}, in getCalleeSavedSpillSlots()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1497 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
|