| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 52 S17(7, 4, 1);
61 S17(7, 5, 1);
134 S17(8, 4, 2);
148 S17(8, 5, 2);
162 S17(8, 6, 2);
216 S17(9, 4, 3);
232 S17(9, 5, 3);
246 S17(9, 6, 3);
258 S17(9, 7, 3);
298 S17(10, 4, 4);
[all …]
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| H A D | usvd_e_t.st | 1 … and i1 <= -5 + i0; S5[i0, i1, 0] : i0 >= 4 and i1 <= 4 and i1 >= -4 + i0; S17[i0, i1, -6 + i0] : …
5 …S17[i0, i1, i2] -> [(i0)]; S25[i0, i1, i2] -> [(i0)]; S18[i0, i1, i2] -> [(i0)]; S26[i0, i1, i2] -…
25 - filter: "{ S17[i0, i1, i2] }"
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| H A D | swim.c | 18 S17();
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| H A D | swim.st | 1 …1 and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= Q and i2 >= 1 and i2 <= R; S17[] : M = 1; S96[i0, …
22 - filter: "[M, N, O, P, Q, R] -> { S17[] }"
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| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | attr-trivial-abi.cpp | 109 struct __attribute__((trivial_abi)) S17 { struct
112 S17<int> s17;
113 static_assert(__is_trivially_relocatable(S17<int>), "");
114 static_assert(__is_trivially_relocatable(S17<S3>), "");
|
| /llvm-project-15.0.7/clang/test/SemaObjCXX/ |
| H A D | attr-trivial-abi.mm | 93 struct __attribute__((trivial_abi)) S17 { // expected-warning {{'trivial_abi' cannot be applied to …
94 S17();
95 S17(S17 &&);
103 S17<int> s17;
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | crash-nosse.ll | 10 %S17 = select i1 true, ptr null, ptr null
14 %L19 = load <8 x float>, ptr %S17
20 store <8 x float> %L19, ptr %S17
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| H A D | 2012-02-14-scalar.ll | 6 %S17 = icmp sgt <1 x i64> undef, undef
7 %E19 = extractelement <1 x i1> %S17, i32 0
|
| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 88 struct S17 { struct
152 S14*, S15*, S16*, S17*, S18*, S19*, S20*, S21*, S22*, S23*, S24*, S25*, in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 76 static S S17; in MultipleStatics() local
|
| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 25 struct S17 { virtual void f(); }; struct
83 S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
|
| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 102 // CHECK-NEXT: %[[S17:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
106 …, "reduction"], kind = #vector.kind<add>} %[[S14]], %[[S15]], %[[S16]], %[[S17]], %[[S18]] : vecto…
223 // CHECK-NEXT: %[[S17:.*]] = vector.extract_strided_slice %arg1 {offsets = [0, 2], sizes = [2, 2], …
226 …arallel", "reduction", "parallel"], kind = #vector.kind<add>} %[[S16]], %[[S17]], %[[S18]], %[[S19…
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 55 case AArch64::S17: in isOdd()
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| H A D | AArch64RegisterInfo.td | 346 def S17 : AArch64Reg<17, "s17", [H17]>, DwarfRegAlias<B17>;
381 def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>;
|
| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 3033 struct S17 { struct
3037 struct S17 { struct
3041 S17 s17;
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 110 def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
129 def D8 : ARMReg< 8, "d8", [S16, S17]>, DwarfRegNum<[264]>;
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| H A D | ARMCallingConv.td | 116 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 266 {codeview::RegisterId::ARM_FS17, ARM::S17}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 155 {codeview::RegisterId::ARM64_S17, AArch64::S17}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 279 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
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| H A D | PPCFrameLowering.cpp | 208 {PPC::S17, -120}, in getCalleeSavedSpillSlots()
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1497 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
|