| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 86 S15(8, 1, 4);
102 S15(8, 2, 4);
113 S15(8, 3, 4);
139 S15(8, 4, 4);
153 S15(8, 5, 4);
196 S15(9, 3, c2);
220 S15(9, 4, c2);
236 S15(9, 5, c2);
272 S15(10, c1, 4);
296 S15(10, 4, 4);
[all …]
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| H A D | usvd_e_t.st | 1 … i1 <= 11; S25[i0, i1, 4] : i0 >= 10 and i0 <= 14 and i1 >= 1 and i1 <= 5; S15[i0, i1, i2] : i0 <=…
5 …S15[i0, i1, i2] -> [(i0)]; S12[i0, i1, i2] -> [(i0)]; S7[i0, i1, i2] -> [(i0)]; S6[i0, i1, i2] -> …
23 - filter: "{ S15[i0, i1, i2] }"
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| H A D | reservoir-mg-interp.st | 1 …nd i0 <= -1 + O and i1 >= 1 and i1 <= -1 + N and i2 >= 1 and i2 <= -1 + M; S15[i0, i1, i2] : i0 >=…
106 - filter: "[M, N, O, P, Q, R, S, T, U] -> { S15[i0, i1, i2] }"
108 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S15[i0, i1, i2] -> [(i0)] }]"
111 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S15[i0, i1, i2] -> [(i1)] }]"
114 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S15[i0, i1, i2] -> [(i2)] }]"
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| H A D | reservoir-mg-interp.c | 83 S15(c0, c1, c2);
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| H A D | swim.c | 16 S15();
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| H A D | swim.st | 1 …1] : M = 1 and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= Q; S22[] : M = 1; S15[] : M = 1; S30[i0, …
20 - filter: "[M, N, O, P, Q, R] -> { S15[] }"
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| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | attr-trivial-abi.cpp | 92 struct __attribute__((trivial_abi)) S15 : S14<T> { struct
95 S15<int> s15;
96 static_assert(__is_trivially_relocatable(S15<int>), "");
97 static_assert(!__is_trivially_relocatable(S15<S3>), "");
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 79 struct S15 { // expected-warning {{packed attribute is unnecessary for 'S15'}} struct
152 S14*, S15*, S16*, S17*, S18*, S19*, S20*, S21*, S22*, S23*, S24*, S25*, in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 74 static S S15; in MultipleStatics() local
|
| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 23 struct S15 { virtual void f(); }; struct
83 S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
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| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | ConcatenatedSubregs.td | 47 def S15 : MyReg<"s15">;
58 def D7 : MyReg<"d7", [S14, S15]>;
84 // CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
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| /llvm-project-15.0.7/clang/test/SemaObjCXX/ |
| H A D | attr-trivial-abi.mm | 80 struct __attribute__((trivial_abi)) S15 : S14<T> {
83 S15<int> s15;
|
| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/misc/ |
| H A D | non-private-member-variables-in-classes.cpp | 300 class S15 { class
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.td | 80 S9, S10, S11, S12, S13, S14, S15]>>,
100 S9, S10, S11, S12, S13, S14, S15]>>,
228 S9, S10, S11, S12, S13, S14, S15]>>,
248 S9, S10, S11, S12, S13, S14, S15]>>,
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| H A D | ARMCallingConv.cpp | 158 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
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| H A D | ARMRegisterInfo.td | 109 def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
128 def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>;
|
| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 53 // CHECK-NEXT: %[[S15:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [2, 2], sizes = [2, 2]…
54 // CHECK-NEXT: %[[A8:.*]] = arith.addf %[[S15]], %[[A4]] : vector<2x2xf32>
103 // CHECK-NEXT: %[[S15:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [0, 2], sizes = [2, 2]…
106 …arallel", "parallel", "reduction"], kind = #vector.kind<add>} %[[S14]], %[[S15]], %[[S16]], %[[S17…
215 // CHECK-NEXT: %[[S15:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
217 …el"], kind = #vector.kind<add>} %[[S11]], %[[S12]], %[[S13]], %[[S14]], %[[S15]] : vector<2x2xf32>…
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| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 633 struct S15 { struct
637 struct S15 { struct
641 S15 s15;
3005 struct S15 { struct
3009 struct S15 { struct
3013 S15 s15;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 54 case AArch64::S15: in isOdd()
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| H A D | AArch64RegisterInfo.td | 344 def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>;
379 def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 304 def S15 : Rs<15, "s15">, DwarfRegNum<[159]>;
381 def S15_14 : Rss<14, "s15:14", [S14, S15]>, DwarfRegNum<[158]>;
600 S11, S12, S13, S14, S15,
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 264 {codeview::RegisterId::ARM_FS15, ARM::S15}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 153 {codeview::RegisterId::ARM64_S15, AArch64::S15}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 279 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 783 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
|