| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 89 S14(8, 2, c2);
92 S14(8, 2, -2);
96 S14(8, 2, -1);
99 S14(8, 2, 0);
105 S14(8, 3, c2);
109 S14(8, 3, -1);
111 S14(8, 3, 0);
120 S14(8, 4, -1);
125 S14(8, 4, 0);
206 S14(9, 4, 0);
[all …]
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| H A D | usvd_e_t.st | 1 …S11[i0, -3 + i0, i2] : i0 <= 10 and i0 >= 7 and i2 <= 4 and i2 >= -7 + i0; S14[i0, i1, i2] : i0 >=…
5 …S14[i0, i1, i2] -> [(i0)]; S19[i0, i1, i2] -> [(i0)]; S20[i0, i1, i2] -> [(i0)]; S11[i0, i1, i2] -…
22 - filter: "{ S14[i0, i1, i2] }"
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| H A D | reservoir-mg-interp.st | 1 …nd i0 <= -1 + O and i1 >= 1 and i1 <= -1 + N and i2 >= 1 and i2 <= -1 + M; S14[i0, i1, i2] : i0 >=…
96 - filter: "[M, N, O, P, Q, R, S, T, U] -> { S14[i0, i1, i2] }"
98 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S14[i0, i1, i2] -> [(i0)] }]"
101 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S14[i0, i1, i2] -> [(i1)] }]"
104 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S14[i0, i1, i2] -> [(i2)] }]"
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| H A D | reservoir-mg-interp.c | 79 S14(c0, c1, c2);
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| H A D | swim.c | 15 S14();
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| H A D | swim.st | 1 … = 1; S30[i0, i1] : M = 1 and i0 >= 1 and i0 <= N and i1 >= 1 and i1 <= N; S14[] : M = 1; S12[] : …
19 - filter: "[M, N, O, P, Q, R] -> { S14[] }"
|
| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 75 struct S14 { // expected-warning {{packed attribute is unnecessary for 'S14'}} struct
80 struct S14 s; argument
152 S14*, S15*, S16*, S17*, S18*, S19*, S20*, S21*, S22*, S23*, S24*, S25*, in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 73 static S S14; in MultipleStatics() local
|
| /llvm-project-15.0.7/clang/test/CodeGen/ |
| H A D | init.c | 249 struct S14 { int a[16]; }; struct
251 void test14(struct S14 *s14) { in test14()
256 *s14 = (struct S14) { { [5 ... 11] = 17 } }; in test14()
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| /llvm-project-15.0.7/clang/test/SemaCXX/ |
| H A D | attr-trivial-abi.cpp | 87 struct S14 { struct
92 struct __attribute__((trivial_abi)) S15 : S14<T> { argument
101 S14<T> a;
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| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | ConcatenatedSubregs.td | 46 def S14 : MyReg<"s14">;
58 def D7 : MyReg<"d7", [S14, S15]>;
84 // CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
125 // CHECK-NEXT: SubReg ssub4 = S14
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| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 22 struct S14 { virtual void f(); }; struct
83 S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
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| /llvm-project-15.0.7/clang/test/SemaObjCXX/ |
| H A D | attr-trivial-abi.mm | 74 struct S14 { struct
80 struct __attribute__((trivial_abi)) S15 : S14<T> { argument
87 S14<T> a;
|
| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/misc/ |
| H A D | non-private-member-variables-in-classes.cpp | 283 struct S14 { struct
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.td | 80 S9, S10, S11, S12, S13, S14, S15]>>,
100 S9, S10, S11, S12, S13, S14, S15]>>,
228 S9, S10, S11, S12, S13, S14, S15]>>,
248 S9, S10, S11, S12, S13, S14, S15]>>,
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| H A D | ARMCallingConv.cpp | 158 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
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| H A D | ARMRegisterInfo.td | 109 def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
128 def D7 : ARMReg< 7, "d7", [S14, S15]>, DwarfRegNum<[263]>;
|
| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 619 struct S14 { struct
623 struct S14 { struct
627 S14 s14;
2480 int S14 {}; variable
2483 int S14 {}; variable
2485 using TemplateParameters::S14;
2991 struct S14 { struct
2995 struct S14 { struct
2999 S14 s14;
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| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 101 // CHECK-NEXT: %[[S14:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [0, 0], sizes = [2, 2]…
106 …ypes = ["parallel", "parallel", "reduction"], kind = #vector.kind<add>} %[[S14]], %[[S15]], %[[S16…
213 // CHECK-NEXT: %[[S14:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
217 …", "parallel"], kind = #vector.kind<add>} %[[S11]], %[[S12]], %[[S13]], %[[S14]], %[[S15]] : vecto…
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 103 case AArch64::S14: in isOdd()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 303 def S14 : Rs<14, "s14">, DwarfRegNum<[158]>;
381 def S15_14 : Rss<14, "s15:14", [S14, S15]>, DwarfRegNum<[158]>;
600 S11, S12, S13, S14, S15,
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 263 {codeview::RegisterId::ARM_FS14, ARM::S14}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 152 {codeview::RegisterId::ARM64_S14, AArch64::S14}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.td | 279 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 782 Hexagon::S12, Hexagon::S13, Hexagon::S14,
|