| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 128 S13(8, 4, 1);
132 S13(8, 4, 2);
136 S13(8, 4, 3);
138 S13(8, 4, 4);
210 S13(9, 4, 2);
214 S13(9, 4, 3);
218 S13(9, 4, 4);
225 S13(9, 5, 2);
230 S13(9, 5, 3);
234 S13(9, 5, 4);
[all …]
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| H A D | usvd_e_t.st | 1 …, i1, i2] : i0 <= 9 and i1 >= 4 and i1 <= 8 and i2 >= 0 and i2 <= -7 + i0; S13[i0, i1, i2] : i0 <=…
5 …S13[i0, i1, i2] -> [(i0)]; S3[i0, i1, i2] -> [(i0)]; S14[i0, i1, i2] -> [(i0)]; S19[i0, i1, i2] ->…
21 - filter: "{ S13[i0, i1, i2] }"
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| H A D | reservoir-mg-interp.st | 1 …nd i0 <= -1 + O and i1 >= 1 and i1 <= -1 + N and i2 >= P and i2 <= -1 + M; S13[i0, i1, i2] : i0 >=…
86 - filter: "[M, N, O, P, Q, R, S, T, U] -> { S13[i0, i1, i2] }"
88 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S13[i0, i1, i2] -> [(i0)] }]"
91 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S13[i0, i1, i2] -> [(i1)] }]"
94 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S13[i0, i1, i2] -> [(i2)] }]"
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| H A D | reservoir-mg-interp.c | 75 S13(c0, c1, c2);
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| H A D | swim.c | 14 S13();
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| H A D | swim.st | 1 …= R; S114[i0, i1] : M = 1 and i0 >= 2 and i0 <= P and i1 >= 1 and i1 <= R; S13[] : M = 1; S72[i0] …
18 - filter: "[M, N, O, P, Q, R] -> { S13[] }"
|
| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | ConcatenatedSubregs.td | 45 def S13 : MyReg<"s13">;
57 def D6 : MyReg<"d6", [S12, S13]>;
84 // CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
112 // CHECK-NEXT: SubReg ssub4 = S13
124 // CHECK-NEXT: SubReg ssub3 = S13
|
| /llvm-project-15.0.7/clang/test/ASTMerge/struct/Inputs/ |
| H A D | struct2.c | 74 } S13; typedef
76 S13 x13;
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| H A D | struct1.c | 77 } S13; typedef
79 S13 x13;
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 70 struct S13 { // expected-warning {{padding size of 'S13' with 6 bits to alignment boundary}} struct
151 void f(S1*, S2*, S3*, S4*, S5*, S6*, S7*, S8*, S9*, S10*, S11*, S12*, S13*, in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 72 static S S13; in MultipleStatics() local
|
| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 21 struct S13 { virtual void f(); }; struct
83 S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
|
| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 370 struct S13 { struct
374 struct S13 { struct
378 S13 s13;
605 struct S13 { struct
609 struct S13 { struct
613 S13 s13;
2470 int S13 {}; variable
2473 int S13 {}; variable
2977 struct S13 { struct
2985 S13 s13;
[all …]
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| /llvm-project-15.0.7/clang/test/SemaObjCXX/ |
| H A D | attr-trivial-abi.mm | 43 struct __attribute__((trivial_abi)) S13 { // expected-warning {{'trivial_abi' cannot be applied to …
|
| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/misc/ |
| H A D | non-private-member-variables-in-classes.cpp | 266 class S13 { class
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.td | 80 S9, S10, S11, S12, S13, S14, S15]>>,
100 S9, S10, S11, S12, S13, S14, S15]>>,
228 S9, S10, S11, S12, S13, S14, S15]>>,
248 S9, S10, S11, S12, S13, S14, S15]>>,
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| H A D | ARMCallingConv.cpp | 158 ARM::S12, ARM::S13, ARM::S14, ARM::S15 };
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| H A D | ARMRegisterInfo.td | 108 def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
127 def D6 : ARMReg< 6, "d6", [S12, S13]>, DwarfRegNum<[262]>;
|
| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 49 // CHECK-NEXT: %[[S13:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [2, 0], sizes = [2, 2]…
50 // CHECK-NEXT: %[[A7:.*]] = arith.addf %[[S13]], %[[A3]] : vector<2x2xf32>
97 // CHECK-NEXT: %[[S13:.*]] = vector.constant_mask [2, 2] : vector<2x2xi1>
98 …"], kind = #vector.kind<add>} %[[S10]], %[[S11]], %[[R2S00]], %[[S12]], %[[S13]] : vector<2x2xf32>…
216 // CHECK-NEXT: %[[S13:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [2, 0], sizes = [2, 2]…
217 …"reduction", "parallel"], kind = #vector.kind<add>} %[[S11]], %[[S12]], %[[S13]], %[[S14]], %[[S15…
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 53 case AArch64::S13: in isOdd()
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| H A D | AArch64RegisterInfo.td | 342 def S13 : AArch64Reg<13, "s13", [H13]>, DwarfRegAlias<B13>;
377 def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>;
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 302 def S13 : Rs<13, "s13">, DwarfRegNum<[157]>;
380 def S13_12 : Rss<12, "s13:12", [S12, S13]>, DwarfRegNum<[156]>;
600 S11, S12, S13, S14, S15,
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 262 {codeview::RegisterId::ARM_FS13, ARM::S13}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 151 {codeview::RegisterId::ARM64_S13, AArch64::S13}, in initLLVMToCVRegMapping()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 782 Hexagon::S12, Hexagon::S13, Hexagon::S14,
|