| /llvm-project-15.0.7/polly/lib/External/isl/test_inputs/codegen/cloog/ |
| H A D | usvd_e_t.c | 47 S11(7, 4, 0);
50 S11(7, 4, 1);
54 S11(7, 4, c2);
141 S11(8, 5, 1);
146 S11(8, 5, 2);
150 S11(8, 5, 3);
152 S11(8, 5, 4);
239 S11(9, 6, 2);
244 S11(9, 6, 3);
248 S11(9, 6, 4);
[all …]
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| H A D | reservoir-mg-interp.c | 19 S11(c0, 1, c3);
24 S11(c0, 1, c3);
38 S11(c0, (c1 + 1) / 2, c3);
46 S11(c0, N - 1, c3);
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| H A D | usvd_e_t.st | 1 …2] : i0 >= 8 and i1 >= 1 and i2 <= 0 and i2 >= -10 + i0 and i1 <= -6 + i0; S11[i0, -3 + i0, i2] : …
5 …S11[i0, i1, i2] -> [(i0)]; S1[i0, i1, i2] -> [(i0)] }, { S8[i0, i1, i2] -> [(i1)]; S21[i0, i1, i2]…
19 - filter: "{ S11[i0, i1, i2] }"
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| H A D | reservoir-mg-interp.st | 1 …nd i0 <= -1 + O and i1 >= 1 and i1 <= -1 + N and i2 >= 1 and i2 <= -1 + M; S11[i0, i1, i2] : i0 >=…
6 …, U] -> { S10[i0, i1, i2]; S6[i0, i1, i2]; S3[i0, i1, i2]; S1[i0, i1, i2]; S11[i0, i1, i2]; S7[i0,…
8 …schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S11[i0, i1, i2] -> [(i0)]; S1[i0, i1, i2] -> [(i0)]; …
11 …schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S11[i0, i1, i2] -> [(2i1)]; S1[i0, i1, i2] -> [(-3 + …
31 - filter: "[M, N, O, P, Q, R, S, T, U] -> { S11[i0, i1, i2] }"
33 schedule: "[M, N, O, P, Q, R, S, T, U] -> [{ S11[i0, i1, i2] -> [(i2)] }]"
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| H A D | swim.c | 12 S11();
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| H A D | swim.st | 1 … >= 2 and i0 <= P; S3[] : M = 1; S100[i0] : M = 1 and i0 >= 2 and i0 <= P; S11[] : M = 1; S76[i0] …
16 - filter: "[M, N, O, P, Q, R] -> { S11[] }"
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| /llvm-project-15.0.7/clang/test/CodeGen/ |
| H A D | arm64-microsoft-arguments.cpp | 194 struct S11 { struct
199 S11 func11(S11 x); argument
200 S11 f11() { in f11()
201 S11 x; in f11()
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| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | ConcatenatedSubregs.td | 43 def S11 : MyReg<"s11">;
56 def D5 : MyReg<"d5", [S10, S11]>;
84 // CHECK: Regs: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15
110 // CHECK-NEXT: SubReg ssub2 = S11
122 // CHECK-NEXT: SubReg ssub1 = S11
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| /llvm-project-15.0.7/clang/test/Modules/ |
| H A D | odr_hash.cpp | 342 struct S11 { struct
346 struct S11 { struct
350 S11 s11;
577 struct S11 { struct
581 struct S11 { struct
585 S11 s11;
834 S11();
837 S11 s11;
1937 S11 s11;
2955 S11 s11;
[all …]
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| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | warn-padded-packed.cpp | 60 struct S11 { // expected-warning {{packed attribute is unnecessary for 'S11'}} struct
151 void f(S1*, S2*, S3*, S4*, S5*, S6*, S7*, S8*, S9*, S10*, S11*, S12*, S13*, in f() argument
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| H A D | microsoft-abi-static-initializers.cpp | 70 static S S11; in MultipleStatics() local
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| /llvm-project-15.0.7/clang/test/PCH/ |
| H A D | cxx-key-functions.cpp | 19 struct S11 { virtual void f(); }; struct
83 S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
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| /llvm-project-15.0.7/clang/test/CodeGen/SystemZ/ |
| H A D | zos-alignment.c | 156 } S11; variable
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| /llvm-project-15.0.7/clang/test/Sema/ |
| H A D | address-packed.c | 323 struct S11 { struct
328 struct S11 __attribute__((__aligned__(4))) a[4]; in g13() argument
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| /llvm-project-15.0.7/clang/test/SemaObjCXX/ |
| H A D | attr-trivial-abi.mm | 51 struct __attribute__((trivial_abi)) S11 { // expected-warning {{'trivial_abi' cannot be applied to …
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| /llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/checkers/misc/ |
| H A D | non-private-member-variables-in-classes.cpp | 230 class S11 { class
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.td | 80 S9, S10, S11, S12, S13, S14, S15]>>,
100 S9, S10, S11, S12, S13, S14, S15]>>,
228 S9, S10, S11, S12, S13, S14, S15]>>,
248 S9, S10, S11, S12, S13, S14, S15]>>,
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| H A D | ARMCallingConv.cpp | 157 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
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| H A D | ARMRegisterInfo.td | 107 def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
126 def D5 : ARMReg< 5, "d5", [S10, S11]>, DwarfRegNum<[261]>;
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| /llvm-project-15.0.7/mlir/test/Dialect/Vector/ |
| H A D | vector-transforms.mlir | 45 // CHECK-NEXT: %[[S11:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [0, 2], sizes = [2, 2]…
46 // CHECK-NEXT: %[[A6:.*]] = arith.addf %[[S11]], %[[A2]] : vector<2x2xf32>
96 // CHECK-NEXT: %[[S11:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [4, 0], sizes = [2, 2]…
98 …arallel", "parallel", "reduction"], kind = #vector.kind<add>} %[[S10]], %[[S11]], %[[R2S00]], %[[S…
212 // CHECK-NEXT: %[[S11:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [2, 0], sizes = [2, 2]…
217 …ypes = ["parallel", "reduction", "parallel"], kind = #vector.kind<add>} %[[S11]], %[[S12]], %[[S13…
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64PBQPRegAlloc.cpp | 52 case AArch64::S11: in isOdd()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 300 def S11 : Rs<11, "s11">, DwarfRegNum<[155]>;
379 def S11_10 : Rss<10, "s11:10", [IMASK, S11]>, DwarfRegNum<[154]>;
600 S11, S12, S13, S14, S15,
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 260 {codeview::RegisterId::ARM_FS11, ARM::S11}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 149 {codeview::RegisterId::ARM64_S11, AArch64::S11}, in initLLVMToCVRegMapping()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 781 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
|