Searched refs:RootDef (Results 1 – 2 of 2) sorted by relevance
6409 if (RootDef.getOpcode() != AArch64::G_ADD_LOW) in tryFoldAddLowIntoImm()6424 auto &MF = *RootDef.getParent()->getParent(); in tryFoldAddLowIntoImm()6429 MachineIRBuilder MIRBuilder(RootDef); in tryFoldAddLowIntoImm()6468 MachineOperand &LHS = RootDef->getOperand(1); in selectAddrModeIndexed()6469 MachineOperand &RHS = RootDef->getOperand(2); in selectAddrModeIndexed()6646 if (!RootDef) in selectArithExtendedRegister()6655 MachineOperand &RHS = RootDef->getOperand(2); in selectArithExtendedRegister()6663 MachineOperand &LHS = RootDef->getOperand(1); in selectArithExtendedRegister()6673 Ext = getExtendTypeForInst(*RootDef, MRI); in selectArithExtendedRegister()6676 ExtReg = RootDef->getOperand(1).getReg(); in selectArithExtendedRegister()[all …]
4290 if (const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg())) { in selectMUBUFScratchOffen() local4305 } else if (RootDef->getOpcode() == AMDGPU::G_FRAME_INDEX) { in selectMUBUFScratchOffen()4306 FI = RootDef->getOperand(1).getIndex(); in selectMUBUFScratchOffen()4440 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDS1Addr1OffsetImpl() local4441 if (!RootDef) in selectDS1Addr1OffsetImpl()4456 } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { in selectDS1Addr1OffsetImpl()4505 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg()); in selectDSReadWrite2Impl() local4506 if (!RootDef) in selectDSReadWrite2Impl()4523 } else if (RootDef->getOpcode() == AMDGPU::G_SUB) { in selectDSReadWrite2Impl()