| /llvm-project-15.0.7/llvm/lib/Target/XCore/ |
| H A D | XCoreRegisterInfo.td | 19 // Ri - 32-bit integer registers 25 def R0 : Ri< 0, "r0">, DwarfRegNum<[0]>; 26 def R1 : Ri< 1, "r1">, DwarfRegNum<[1]>; 27 def R2 : Ri< 2, "r2">, DwarfRegNum<[2]>; 28 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>; 29 def R4 : Ri< 4, "r4">, DwarfRegNum<[4]>; 30 def R5 : Ri< 5, "r5">, DwarfRegNum<[5]>; 31 def R6 : Ri< 6, "r6">, DwarfRegNum<[6]>; 32 def R7 : Ri< 7, "r7">, DwarfRegNum<[7]>; 33 def R8 : Ri< 8, "r8">, DwarfRegNum<[8]>; [all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 215 def C0 : Ri< 0, "C0">; 216 def C1 : Ri< 1, "C1">; 217 def C2 : Ri< 2, "C2">; 218 def C3 : Ri< 3, "C3">; 219 def C4 : Ri< 4, "C4">; 220 def C5 : Ri< 5, "C5">; 221 def C6 : Ri< 6, "C6">; 222 def C7 : Ri< 7, "C7">; 223 def C8 : Ri< 8, "C8">; 224 def C9 : Ri< 9, "C9">; [all …]
|
| /llvm-project-15.0.7/llvm/lib/Transforms/IPO/ |
| H A D | DeadArgumentElimination.cpp | 397 for (unsigned Ri = 0; Ri < numRetVals(F); ++Ri) { in surveyUse() local 398 RetOrArg Use = createRet(F, Ri); in surveyUse() 590 for (unsigned Ri = 0; Ri != RetCount; ++Ri) { in surveyFunction() local 591 if (RetValLiveness[Ri] != Live) in surveyFunction() 605 for (unsigned Ri = 0; Ri != RetCount; ++Ri) in surveyFunction() local 606 markValue(createRet(&F, Ri), RetValLiveness[Ri], MaybeLiveRetUses[Ri]); in surveyFunction() 681 for (unsigned Ri = 0, E = numRetVals(&F); Ri != E; ++Ri) in markLive() local 793 for (unsigned Ri = 0; Ri != RetCount; ++Ri) { in removeDeadStuffFromFunction() local 794 RetOrArg Ret = createRet(F, Ri); in removeDeadStuffFromFunction() 970 for (unsigned Ri = 0; Ri != RetCount; ++Ri) in removeDeadStuffFromFunction() local [all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/BPF/ |
| H A D | BPFRegisterInfo.td | 23 // Ri - 64-bit integer registers 24 class Ri<bits<16> Enc, string n, list<Register> subregs> 35 def R#I : Ri<I, "r"#I, [!cast<Wi>("W"#I)]>, DwarfRegNum<[I]>;
|
| /llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/ |
| H A D | interfaces-global-init.rst | 10 https://github.com/isocpp/CppCoreGuidelines/blob/master/CppCoreGuidelines.md#Ri-global-init
|
| H A D | avoid-non-const-global-variables.rst | 6 …elines <https://github.com/isocpp/CppCoreGuidelines/blob/master/CppCoreGuidelines.md#Ri-global>`_ .
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 48 // Ri - 32-bit integer registers. 49 class Ri<bits<5> num, string n, list<string> alt = []> : 129 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>; 131 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>; 132 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; 133 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>; 224 def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>; 228 def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>;
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | WritingAnLLVMBackend.rst | 424 a ``Register`` subclass, ``SparcReg``, and further subclasses: ``Ri``, ``Rf``, 436 // Ri - 32-bit integer registers 437 class Ri<bits<5> num, string n> : 457 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 458 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 5450 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), 5451 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>; 5452 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), 5453 (TBLv16i8One V128:$Ri, V128:$Rn)>; 5456 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))), 5457 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>; 5459 (v16i8 V128:$Ri), (v16i8 V128:$Rn))), 5460 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
|