Searched refs:Rg (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 107 // Rg - Guest/Hypervisor registers
108 class Rg<bits<5> num, string n,
417 def GELR: Rg<0, "gelr", ["g0"]>, DwarfRegNum<[220]>;
418 def GSR: Rg<1, "gsr", ["g1"]>, DwarfRegNum<[221]>;
419 def GOSP: Rg<2, "gosp", ["g2"]>, DwarfRegNum<[222]>;
420 def G3: Rg<3, "gbadva", ["g3"]>, DwarfRegNum<[223]>;
421 def G4: Rg<4, "g4">, DwarfRegNum<[224]>;
422 def G5: Rg<5, "g5">, DwarfRegNum<[225]>;
423 def G6: Rg<6, "g6">, DwarfRegNum<[226]>;
424 def G7: Rg<7, "g7">, DwarfRegNum<[227]>;
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| H A D | HexagonBlockRanges.cpp | 146 IndexRange &Rg = *I; in subtract() local
147 if (Rg.overlaps(Range)) { in subtract()
148 T.addsub(Rg, Range); in subtract()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | SwitchLoweringUtils.h | 223 BitTestBlock(APInt F, APInt R, const Value *SV, unsigned Rg, MVT RgVT, bool E, in BitTestBlock()
226 : First(std::move(F)), Range(std::move(R)), SValue(SV), Reg(Rg), in BitTestBlock()
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