| /llvm-project-15.0.7/llvm/unittests/ADT/ |
| H A D | SequenceTest.cpp | 108 EXPECT_EQ(Reverse, Reverse); in TEST()
109 EXPECT_LT(Reverse - 1, Reverse); in TEST()
110 EXPECT_LE(Reverse, Reverse); in TEST()
111 EXPECT_LE(Reverse - 1, Reverse); in TEST()
112 EXPECT_GT(Reverse + 1, Reverse); in TEST()
113 EXPECT_GE(Reverse, Reverse); in TEST()
114 EXPECT_GE(Reverse + 1, Reverse); in TEST()
130 ++Reverse; in TEST()
177 EXPECT_EQ(Reverse - Reverse, 0); in TEST()
180 EXPECT_EQ((Reverse + 1) - Reverse, 1); in TEST()
[all …]
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| H A D | IteratorTest.cpp | 514 TEST(ZipIteratorTest, Reverse) { in TEST() argument
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| /llvm-project-15.0.7/clang/lib/AST/ |
| H A D | ExternalASTMerger.cpp | 102 ASTImporter Reverse; member in __anon14fbbf8e0111::LazyASTImporter
244 ASTImporter &GetReverse() { return Reverse; } in GetReverse()
291 ASTImporter &Reverse = in ForEachMatchingDC() local
293 if (auto SourceDC = LookupSameContext(SourceTU, DC, Reverse)) { in ForEachMatchingDC()
295 if (Callback(*Importer, Reverse, SourceDC)) in ForEachMatchingDC()
328 Interface, [&](ASTImporter &Forward, ASTImporter &Reverse, in CompleteType() argument
349 [&](ASTImporter &Forward, ASTImporter &Reverse, in CanComplete() argument
372 ASTImporter &Reverse = Importer.GetReverse(); in MaybeRecordOrigin() local
488 [&](ASTImporter &Forward, ASTImporter &Reverse, in FindExternalVisibleDeclsByName()
490 auto FromNameOrErr = Reverse.Import(Name); in FindExternalVisibleDeclsByName()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/Analysis/ |
| H A D | VectorUtils.h | 611 InterleaveGroup(uint32_t Factor, bool Reverse, Align Alignment) in InterleaveGroup() argument
612 : Factor(Factor), Reverse(Reverse), Alignment(Alignment), in InterleaveGroup()
620 Reverse = Stride < 0; in InterleaveGroup()
624 bool isReverse() const { return Reverse; } in isReverse()
723 bool Reverse; variable
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | VarLenCodeEmitterGen.cpp | 102 bool Reverse = Op == "descend"; in buildRec() local
103 int i = Reverse ? DI->getNumArgs() - 1 : 0; in buildRec()
104 int e = Reverse ? -1 : DI->getNumArgs(); in buildRec()
105 int s = Reverse ? -1 : 1; in buildRec()
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| /llvm-project-15.0.7/lldb/docs/use/ |
| H A D | links.rst | 56 `Advanced Apple Debugging & Reverse Engineering (2018)`_
80 .. _Advanced Apple Debugging & Reverse Engineering (2018): https://www.raywenderlich.com/books/adva…
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| /llvm-project-15.0.7/llvm/lib/TableGen/ |
| H A D | SetTheory.cpp | 124 const bool Reverse; member
126 RotOp(bool Rev) : Reverse(Rev) {} in RotOp()
130 if (Reverse) in apply2()
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| /llvm-project-15.0.7/flang/unittests/Evaluate/ |
| H A D | integer.cpp | 245 TEST(Reverse(Ordering::Less) == Ordering::Greater); in main()
246 TEST(Reverse(Ordering::Greater) == Ordering::Less); in main()
247 TEST(Reverse(Ordering::Equal) == Ordering::Equal); in main()
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| /llvm-project-15.0.7/flang/include/flang/Evaluate/ |
| H A D | common.h | 70 static constexpr Ordering Reverse(Ordering ordering) { in Reverse() function
90 static constexpr Relation Reverse(Relation relation) { in Reverse() function
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| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlan.h | 1715 bool Reverse; variable
1729 bool Consecutive, bool Reverse) in VPWidenMemoryInstructionRecipe() argument
1731 Consecutive(Consecutive), Reverse(Reverse) {
1732 assert((Consecutive || !Reverse) && "Reverse implies consecutive");
1739 bool Consecutive, bool Reverse) in VPWidenMemoryInstructionRecipe() argument
1741 Ingredient(Store), Consecutive(Consecutive), Reverse(Reverse) {
1742 assert((Consecutive || !Reverse) && "Reverse implies consecutive");
1777 bool isReverse() const { return Reverse; } in isReverse()
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| /llvm-project-15.0.7/polly/lib/Transform/ |
| H A D | MaximalStaticExpansion.cpp | 291 bool Reverse) { in mapAccess() argument
302 filterDependences(Reverse ? Dependences.reverse() : Dependences, MA); in mapAccess()
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| /llvm-project-15.0.7/llvm/unittests/IR/ |
| H A D | InstructionsTest.cpp | 1037 Constant *Reverse = ConstantVector::get({C3, C2, C1, CU}); in TEST() local
1038 EXPECT_FALSE(ShuffleVectorInst::isIdentityMask(Reverse)); in TEST()
1039 EXPECT_FALSE(ShuffleVectorInst::isSelectMask(Reverse)); in TEST()
1040 EXPECT_TRUE(ShuffleVectorInst::isReverseMask(Reverse)); in TEST()
1041 EXPECT_TRUE(ShuffleVectorInst::isSingleSourceMask(Reverse)); // reverse is always single source in TEST()
1042 EXPECT_FALSE(ShuffleVectorInst::isZeroEltSplatMask(Reverse)); in TEST()
1043 EXPECT_FALSE(ShuffleVectorInst::isTransposeMask(Reverse)); in TEST()
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| /llvm-project-15.0.7/polly/include/polly/Support/ |
| H A D | ISLTools.h | 339 isl::union_map Writes, bool Reverse,
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| /llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/ |
| H A D | int-cmp-45.ll | 36 ; Reverse the select order and test with LOCR.
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| /llvm-project-15.0.7/polly/lib/Support/ |
| H A D | ISLTools.cpp | 302 isl::union_map Writes, bool Reverse, in computeReachingWrite() argument
310 if (Reverse) in computeReachingWrite()
333 if (Reverse) in computeReachingWrite()
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| /llvm-project-15.0.7/clang/include/clang/Analysis/Analyses/ |
| H A D | ThreadSafetyCommon.h | 420 CallingContext *Ctx, bool Reverse = false);
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| /llvm-project-15.0.7/clang/lib/Analysis/ |
| H A D | ThreadSafetyCommon.cpp | 506 CallingContext *Ctx, bool Reverse) { in translateBinOp() argument
509 if (Reverse) in translateBinOp()
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| /llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | shuffle-reverse.ll | 8 ;; Reverse shuffles should be lowered to vrev and possibly a vext (for quadwords, on neon)
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| /llvm-project-15.0.7/llvm/docs/GlobalISel/ |
| H A D | GenericOpcode.rst | 229 Reverse the order of the bytes in a scalar.
238 Reverse the order of the bits in a scalar.
|
| /llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/modernize/ |
| H A D | loop-convert.rst | 121 Reverse Iterator Support
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | Lexicon.rst | 273 Reverse postorder
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| /llvm-project-15.0.7/llvm/test/Analysis/CostModel/SystemZ/ |
| H A D | shuffle.ll | 6 ;; Reverse shuffles
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 328 Reverse enumerator
398 getControls(V, 0, Reverse); in run()
414 getControls(R, Log, Reverse); in run()
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| /llvm-project-15.0.7/bolt/test/X86/ |
| H A D | bug-reorder-bb-jrcxz.s | 3 # follow options: None, Normal or Reverse. Other strategies
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| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCWin64EH.cpp | 569 bool Reverse) { in simplifyARM64Opcodes() argument
621 if (Reverse) { in simplifyARM64Opcodes()
|