Searched refs:ResultLo (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 3522 auto ResultLo = B.buildFPTOUI(S32, Mad2); in emitReciprocalU64() local
3525 return {ResultLo.getReg(0), ResultHi.getReg(0)}; in emitReciprocalU64()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 1270 SDNode *ResultLo = in selectI64ImmDirectPrefix() local
1272 SDValue Ops[] = {SDValue(ResultLo, 0), SDValue(ResultHi, 0), getI32Imm(32), in selectI64ImmDirectPrefix()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 11826 SDValue ResultLo = DAG.getNode(Op.getOpcode(), dl, WidenedVT, Op0Lo, Op1Lo); in LowerDIV() local
11828 return DAG.getNode(AArch64ISD::UZP1, dl, VT, ResultLo, ResultHi); in LowerDIV()
21187 SDValue ResultLo = DAG.getNode(Op.getOpcode(), dl, FixedWidenedVT, in LowerFixedLengthVectorIntDivideToSVE() local
21193 ResultLo = convertToScalableVector(DAG, ScalableWidenedVT, ResultLo); in LowerFixedLengthVectorIntDivideToSVE()
21196 ResultLo, ResultHi); in LowerFixedLengthVectorIntDivideToSVE()
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