| /llvm-project-15.0.7/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 64 RegisterFile::RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri, in RegisterFile() function in llvm::mca::RegisterFile
100 void RegisterFile::cycleStart() { in cycleStart()
105 void RegisterFile::onInstructionExecuted(Instruction *IS) { in onInstructionExecuted()
147 void RegisterFile::addRegisterFile(const MCRegisterFileDesc &RF, in addRegisterFile()
228 void RegisterFile::addRegisterWrite(WriteRef Write, in addRegisterWrite()
332 void RegisterFile::removeRegisterWrite( in removeRegisterWrite()
502 void RegisterFile::collectWrites( in collectWrites()
567 RegisterFile::RAWHazard
568 RegisterFile::checkRAWHazards(const MCSubtargetInfo &STI, in checkRAWHazards()
618 void RegisterFile::addRegisterRead(ReadState &RS, in addRegisterRead()
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| /llvm-project-15.0.7/llvm/include/llvm/MCA/Stages/ |
| H A D | InOrderIssueStage.h | 25 class RegisterFile; variable
56 RegisterFile &PRF;
115 InOrderIssueStage(const MCSubtargetInfo &STI, RegisterFile &PRF,
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| H A D | RetireStage.h | 31 RegisterFile &PRF;
38 RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS) in RetireStage()
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| H A D | DispatchStage.h | 56 RegisterFile &PRF;
70 RegisterFile &F);
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| /llvm-project-15.0.7/llvm/lib/MCA/ |
| H A D | Context.cpp | 41 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); in createDefaultPipeline()
76 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); in createInOrderPipeline()
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| H A D | CMakeLists.txt | 8 HardwareUnits/RegisterFile.cpp
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| /llvm-project-15.0.7/llvm/lib/MCA/Stages/ |
| H A D | InOrderIssueStage.cpp | 47 RegisterFile &PRF, CustomBehaviour &CB, in InOrderIssueStage()
103 static unsigned checkRegisterHazard(const RegisterFile &PRF, in checkRegisterHazard()
107 RegisterFile::RAWHazard Hazard = PRF.checkRAWHazards(STI, RS); in checkRegisterHazard()
156 static void addRegisterReadWrite(RegisterFile &PRF, Instruction &IS, in addRegisterReadWrite()
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| H A D | DispatchStage.cpp | 31 RegisterFile &F) in DispatchStage()
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| /llvm-project-15.0.7/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | RegisterFile.h | 83 class RegisterFile : public HardwareUnit {
232 RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
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| /llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/MCA/ |
| H A D | BUILD.gn | 16 "HardwareUnits/RegisterFile.cpp",
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ScheduleBtVer2.td | 50 def JIntegerPRF : RegisterFile<64, [GR64, CCR], [1, 1], [1, 0],
63 def JFpuPRF: RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2], [1, 1, 0],
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| H A D | X86ScheduleBdVer2.td | 98 def PdIntegerPRF : RegisterFile<96, [GR64, CCR]>;
115 def PdFpuPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
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| H A D | X86ScheduleZnver1.td | 102 def ZnIntegerPRF : RegisterFile<168, [GR64, CCR]>;
112 def ZnFpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
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| H A D | X86ScheduleZnver2.td | 103 def Zn2IntegerPRF : RegisterFile<168, [GR64, CCR]>;
113 def Zn2FpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>;
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| H A D | X86ScheduleZnver3.td | 161 def Zn3IntegerPRF : RegisterFile<192, [GR64, CCR], [1, 1], [1, 0],
339 def Zn3FpPRF : RegisterFile<160, [VR64, VR128, VR256], [1, 1, 1], [0, 1, 1],
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetSchedule.td | 538 class RegisterFile<int numPhysRegs, list<RegisterClass> Classes = [],
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| /llvm-project-15.0.7/clang/docs/tools/ |
| H A D | clang-formatted-files.txt | 5402 llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h
6127 llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
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