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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h99 IndexedMap<std::pair<Register, SmallVector<Register, 4>>,
606 void replaceRegWith(Register FromReg, Register ToReg);
717 bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
736 Register cloneVirtualRegister(Register VReg, StringRef Name = "");
782 void addRegAllocationHint(Register VReg, Register PrefReg) { in addRegAllocationHint()
789 void setSimpleHint(Register VReg, Register PrefReg) { in setSimpleHint()
802 std::pair<Register, Register>
813 Register getSimpleHint(Register VReg) const { in getSimpleHint()
815 std::pair<Register, Register> Hint = getRegAllocationHint(VReg); in getSimpleHint()
821 const std::pair<Register, SmallVector<Register, 4>>
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H A DVirtRegMap.h99 bool hasPhys(Register virtReg) const { in hasPhys()
105 MCRegister getPhys(Register virtReg) const { in getPhys()
116 bool hasShape(Register virtReg) const { in hasShape()
120 ShapeT getShape(Register virtReg) const { in getShape()
131 void clearVirt(Register virtReg) { in clearVirt()
153 void setIsSplitFromReg(Register virtReg, Register SReg) { in setIsSplitFromReg()
161 Register getPreSplitReg(Register virtReg) const { in getPreSplitReg()
169 Register getOriginal(Register VirtReg) const { in getOriginal()
170 Register Orig = getPreSplitReg(VirtReg); in getOriginal()
187 int getStackSlot(Register virtReg) const { in getStackSlot()
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H A DFunctionLoweringInfo.h69 Register DemoteRegister;
77 DenseMap<const Value *, Register> ValueMap;
84 DenseMap<Register, const Value*> VirtReg2Value;
88 const Value *getValueFromVirtualReg(Register Vreg);
114 Register Reg;
142 DenseMap<Register, Register> RegFixups;
144 DenseSet<Register> RegsWithFixups;
204 Register CreateRegs(const Value *V);
208 Register InitializeRegForValue(const Value *V) { in InitializeRegForValue()
212 Register &R = ValueMap[V]; in InitializeRegForValue()
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H A DLiveVariables.h109 bool isLiveIn(const MachineBasicBlock &MBB, Register Reg,
152 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
157 void HandlePhysRegUse(Register Reg, MachineInstr &MI);
158 void HandlePhysRegDef(Register Reg, MachineInstr *MI,
164 MachineInstr *FindLastRefOrPartRef(Register Reg);
169 MachineInstr *FindLastPartialDef(Register Reg,
196 void recomputeForSingleDefVirtReg(Register Reg);
277 VarInfo &getVarInfo(Register Reg);
285 void HandleVirtRegDef(Register reg, MachineInstr &MI);
288 bool isLiveIn(Register Reg, const MachineBasicBlock &MBB) { in isLiveIn()
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H A DRegister.h19 class Register {
23 constexpr Register(unsigned Val = 0): Reg(Val) {} in Reg()
24 constexpr Register(MCRegister Val): Reg(Val) {} in Register() function
52 static int stackSlot2Index(Register Reg) { in stackSlot2Index()
58 static Register index2StackSlot(int FI) { in index2StackSlot()
60 return Register(FI + MCRegister::FirstStackSlot); in index2StackSlot()
77 static unsigned virtReg2Index(Register Reg) { in virtReg2Index()
84 static Register index2VirtReg(unsigned Index) { in index2VirtReg()
148 template<> struct DenseMapInfo<Register> {
155 static unsigned getHashValue(const Register &Val) {
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H A DLiveRangeEdit.h57 virtual bool LRE_CanEraseVirtReg(Register) { return true; } in LRE_CanEraseVirtReg() argument
60 virtual void LRE_WillShrinkVirtReg(Register) {} in LRE_WillShrinkVirtReg() argument
64 virtual void LRE_DidCloneVirtReg(Register New, Register Old) {} in LRE_DidCloneVirtReg()
69 SmallVectorImpl<Register> &NewRegs;
109 void MRI_NoteNewVirtualRegister(Register VReg) override;
147 Register getReg() const { return getParent().reg(); } in getReg()
150 using iterator = SmallVectorImpl<Register>::const_iterator;
167 ArrayRef<Register> regs() const { in regs()
172 Register createFrom(Register OldReg);
180 Register create() { return createFrom(getReg()); } in create()
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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h55 Register Addr;
56 Register Base;
57 Register Offset;
63 Register Base;
68 Register Reg;
84 Register WideSrcVal;
410 std::pair<Register, Register> &MatchInfo);
412 std::pair<Register, Register> &MatchInfo);
484 std::tuple<Register, Register> &MatchInfo);
486 std::tuple<Register, Register> &MatchInfo);
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H A DUtils.h145 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
169 Optional<APInt> getIConstantVRegVal(Register VReg,
180 Register VReg;
186 getIConstantVRegValWithLookThrough(Register VReg,
198 Register VReg;
204 getFConstantVRegValWithLookThrough(Register VReg,
221 Register Reg;
235 MachineInstr *getDefIgnoringCopies(Register Reg,
244 Register getSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
353 Register Reg;
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H A DCallLowering.h118 Register SwiftErrorVReg;
143 Register DemoteRegister;
265 virtual void assignValueToReg(Register ValVReg, Register PhysReg,
271 virtual void assignValueToAddress(Register ValVReg, Register Addr,
302 copyArgumentMemory(const ArgInfo &Arg, Register DstPtr, Register SrcPtr,
309 Register extendRegister(Register ValReg, CCValAssign &VA,
321 Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
324 void assignValueToReg(Register ValVReg, Register PhysReg,
446 ArrayRef<Register> VRegs, Register DemoteReg,
452 ArrayRef<Register> VRegs, Register DemoteReg) const;
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H A DLegalizerHelper.h127 Register coerceToScalar(Register Val);
211 void insertParts(Register DstReg, LLT ResultTy,
216 void mergeMixedSubvectors(Register DstReg, ArrayRef<Register> PartRegs);
218 void appendVectorElts(SmallVectorImpl<Register> &Elts, Register Reg);
225 LLT NarrowTy, Register SrcReg);
231 Register SrcReg);
272 LegalizeResult lowerMemset(MachineInstr &MI, Register Dst, Register Val,
275 LegalizeResult lowerMemcpyInline(MachineInstr &MI, Register Dst, Register Src,
278 LegalizeResult lowerMemcpy(MachineInstr &MI, Register Dst, Register Src,
281 LegalizeResult lowerMemmove(MachineInstr &MI, Register Dst, Register Src,
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H A DGISelKnownBits.h36 SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
38 void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
42 unsigned computeNumSignBitsMin(Register Src0, Register Src1,
63 unsigned computeNumSignBits(Register R, unsigned Depth = 0);
66 KnownBits getKnownBits(Register R);
67 KnownBits getKnownBits(Register R, const APInt &DemandedElts,
72 APInt getKnownZeroes(Register R);
73 APInt getKnownOnes(Register R);
78 bool maskedValueIsZero(Register Val, const APInt &Mask) { in maskedValueIsZero()
84 bool signBitIsZero(Register Op);
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H A DLegalizationArtifactCombiner.h67 Register TruncSrc; in tryCombineAnyExt()
81 Register ExtSrc; in tryCombineAnyExt()
122 Register TruncSrc; in tryCombineZExt()
123 Register SextSrc; in tryCombineZExt()
145 Register ZextSrc; in tryCombineZExt()
200 Register ExtSrc; in tryCombineSExt()
516 static void replaceRegOrBuildCopy(Register DstReg, Register SrcReg, in replaceRegOrBuildCopy()
562 Register CurrentBest = Register();
725 Register findValueFromDefImpl(Register DefReg, unsigned StartBit, in findValueFromDefImpl()
773 Register findValueFromDef(Register DefReg, unsigned StartBit, in findValueFromDef()
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/llvm-project-15.0.7/llvm/unittests/CodeGen/GlobalISel/
H A DKnownBitsTest.cpp78 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
112 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
150 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
187 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
226 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
1140 Register SrcReg; in TEST_F()
1207 Register CopyReg = Copies[Idx]; in TEST_F()
1278 Register CopyReg = Copies[Idx]; in TEST_F()
1639 Register SrcReg; in TEST_F()
1701 Register SrcReg; in TEST_F()
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H A DKnownBitsVectorTest.cpp33 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
74 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
110 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
146 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
184 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
216 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
254 Register CopyReg = Copies[Copies.size() - 1]; in TEST_F()
1050 Register SrcReg; in TEST_F()
1120 Register CopyReg = Copies[Idx]; in TEST_F()
1188 Register CopyReg = Copies[Idx]; in TEST_F()
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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.h49 Register SrcReg,
50 DenseMap<SDValue, Register> &VRBaseMap);
56 DenseMap<SDValue, Register> &VRBaseMap);
60 Register getVR(SDValue Op,
61 DenseMap<SDValue, Register> &VRBaseMap);
70 DenseMap<SDValue, Register> &VRBaseMap,
81 DenseMap<SDValue, Register> &VRBaseMap,
87 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT,
141 DenseMap<SDValue, Register> &VRBaseMap) { in EmitNode()
162 DenseMap<SDValue, Register> &VRBaseMap);
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/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Dx86_isel.ll.expected9 ; PIC-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0
11 ; PIC-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
18 ; WIN-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0
20 ; WIN-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
33 ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0
36 ; PIC-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8
43 ; WIN-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0
60 ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0
72 ; WIN-NEXT: t2: i16,ch = CopyFromReg t0, Register:i16 %0
90 ; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0
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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp63 void MachineSSAUpdater::Initialize(Register V) { in Initialize()
89 return Register(); in LookForIdenticalPHI()
93 return Register(); in LookForIdenticalPHI()
112 return Register(); in LookForIdenticalPHI()
159 return Register(); in GetValueInMiddleOfBlock()
170 Register SingularValue; in GetValueInMiddleOfBlock()
182 SingularValue = Register(); in GetValueInMiddleOfBlock()
196 return Register(); in GetValueInMiddleOfBlock()
236 Register NewVR; in RewriteUse()
255 using ValT = Register;
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H A DRegAllocGreedy.h91 void setStage(Register Reg, LiveRangeStage Stage) { in setStage()
102 LiveRangeStage getOrInitStage(Register Reg) { in getOrInitStage()
109 void setCascade(Register Reg, unsigned Cascade) { in setCascade()
114 unsigned getOrAssignNewCascade(Register Reg) { in getOrAssignNewCascade()
133 Register Reg = *Begin; in setStage()
139 void LRE_DidCloneVirtReg(Register New, Register Old);
311 bool LRE_CanEraseVirtReg(Register) override;
312 void LRE_WillShrinkVirtReg(Register) override;
313 void LRE_DidCloneVirtReg(Register, Register) override;
378 Register Reg;
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H A DMachineRegisterInfo.cpp61 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank()
145 Register Reg = Register::index2VirtReg(getNumVirtRegs()); in createIncompleteVirtualRegister()
155 Register
170 Register MachineRegisterInfo::cloneVirtualRegister(Register VReg, in cloneVirtualRegister()
185 Register
203 Register Reg = Register::index2VirtReg(i); in clearVirtRegs()
256 verifyUseList(Register::index2VirtReg(i)); in verifyUseLists()
378 void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) { in replaceRegWith()
385 if (Register::isPhysicalRegister(ToReg)) { in replaceRegWith()
454 return Register(); in getLiveInVirtReg()
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/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVGlobalRegistry.h66 void add(const Constant *C, MachineFunction *MF, Register R) { in add()
74 void add(const Function *F, MachineFunction *MF, Register R) { in add()
82 Register find(const Constant *C, MachineFunction *MF) { in find()
86 Register find(const GlobalVariable *GV, MachineFunction *MF) { in find()
90 Register find(const Function *F, MachineFunction *MF) { in find()
113 void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg,
134 SPIRVType *getSPIRVTypeForVReg(Register VReg) const;
137 bool hasSPIRVTypeForVReg(Register VReg) const { in hasSPIRVTypeForVReg()
142 Register getSPIRVTypeID(const SPIRVType *SpirvType) const;
206 Register getOrCreateConstInt(uint64_t Val, MachineInstr &I,
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H A DSPIRVModuleAnalysis.h44 using LocalToGlobalRegTable = std::map<Register, Register>;
57 DenseMap<unsigned, Register> ExtInstSetMap;
61 StringMap<Register> FuncNameMap;
77 DenseMap<int, Register> BBNumToRegMap;
79 Register getFuncReg(std::string FuncName) { in getFuncReg()
90 void setRegisterAlias(const MachineFunction *MF, Register Reg, in setRegisterAlias()
91 Register AliasReg) { in setRegisterAlias()
94 Register getRegisterAlias(const MachineFunction *MF, Register Reg) { in getRegisterAlias()
97 return Register(0); in getRegisterAlias()
110 Register getOrCreateMBBRegister(const MachineBasicBlock &MBB) { in getOrCreateMBBRegister()
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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsgpr-regalloc-flags.ll18 ; DEFAULT: Greedy Register Allocator
19 ; DEFAULT-NEXT: Virtual Register Rewriter
21 ; DEFAULT-NEXT: Virtual Register Map
22 ; DEFAULT-NEXT: Live Register Matrix
23 ; DEFAULT-NEXT: Greedy Register Allocator
25 ; DEFAULT-NEXT: Virtual Register Rewriter
28 ; O0: Fast Register Allocator
30 ; O0-NEXT: Fast Register Allocator
74 ; BASIC-BASIC-NEXT: Virtual Register Map
75 ; BASIC-BASIC-NEXT: Live Register Matrix
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/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h40 Register getSegmentAperture(unsigned AddrSpace,
93 ArrayRef<Register> Src0, ArrayRef<Register> Src1,
100 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
103 bool loadInputValue(Register DstReg, MachineIRBuilder &B,
122 Register DstRemReg, Register Num,
123 Register Den) const;
126 Register DstRemReg, Register Num,
127 Register Den) const;
159 bool getLDSKernelId(Register DstReg, MachineRegisterInfo &MRI,
171 Register SOffset, unsigned ImmOffset, Register VIndex,
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/llvm-project-15.0.7/llvm/test/TableGen/
H A DTargetInstrSpec.td38 class Register<string n> {
47 def XMM0: Register<"xmm0">;
48 def XMM1: Register<"xmm1">;
49 def XMM2: Register<"xmm2">;
50 def XMM3: Register<"xmm3">;
51 def XMM4: Register<"xmm4">;
52 def XMM5: Register<"xmm5">;
53 def XMM6: Register<"xmm6">;
54 def XMM7: Register<"xmm7">;
55 def XMM8: Register<"xmm8">;
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H A Dcast.td37 class Register<string n> {
46 def XMM0: Register<"xmm0">;
47 def XMM1: Register<"xmm1">;
48 def XMM2: Register<"xmm2">;
49 def XMM3: Register<"xmm3">;
50 def XMM4: Register<"xmm4">;
51 def XMM5: Register<"xmm5">;
52 def XMM6: Register<"xmm6">;
53 def XMM7: Register<"xmm7">;
54 def XMM8: Register<"xmm8">;
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