Home
last modified time | relevance | path

Searched refs:RegionBegin (Results 1 – 12 of 12) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DGCNIterativeScheduler.cpp186 assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End); in schedule()
194 Rgn.Begin = Sch.RegionBegin; in schedule()
199 assert(Sch.RegionBegin == Rgn.Begin && Sch.RegionEnd == Rgn.End); in restoreOrder()
298 LLVM_DEBUG(printLivenessInfo(dbgs(), RegionBegin, RegionEnd, LIS); in schedule()
299 if (!Regions.empty() && Regions.back()->Begin == RegionBegin) { in schedule()
358 assert(RegionBegin == R.Begin && RegionEnd == R.End); in scheduleRegion()
388 RegionBegin = getMachineInstr(Schedule.front()); in scheduleRegion()
399 R.Begin = RegionBegin; in scheduleRegion()
H A DGCNSchedStrategy.cpp329 Regions.push_back(std::make_pair(RegionBegin, RegionEnd)); in schedule()
457 RegionBegin = Region.first; in runSchedStages()
576 if (DAG.RegionBegin->getParent() != CurrentMBB) in initGCNRegion()
648 CurrentMBB = DAG.RegionBegin->getParent(); in setupNewBlock()
657 DAG.Regions[RegionIdx] = std::make_pair(DAG.RegionBegin, DAG.RegionEnd); in finalizeGCNRegion()
821 DAG.RegionEnd = DAG.RegionBegin; in revertScheduling()
866 DAG.RegionBegin = Unsched.front()->getIterator(); in revertScheduling()
867 if (DAG.RegionBegin->isDebugInstr()) { in revertScheduling()
871 DAG.RegionBegin = MI->getIterator(); in revertScheduling()
880 DAG.Regions[RegionIdx] = std::make_pair(DAG.RegionBegin, DAG.RegionEnd); in revertScheduling()
H A DSIMachineScheduler.h445 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false); in initRPTracker()
H A DSIMachineScheduler.cpp1986 assert(TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker"); in schedule()
/llvm-project-15.0.7/compiler-rt/lib/scudo/standalone/
H A Dprimary64.h256 B.RegionBegin = RegionInfoArray[ClassId].RegionBeg; in findNearestBlock()
257 B.RegionEnd = B.RegionBegin + RegionInfoArray[ClassId].AllocatedUser; in findNearestBlock()
260 B.RegionBegin + uptr(sptr(Ptr - B.RegionBegin) / sptr(B.BlockSize) * in findNearestBlock()
262 while (B.BlockBegin < B.RegionBegin) in findNearestBlock()
H A Dcommon.h186 uptr RegionBegin; member
H A Dcombined.h1328 if (BlockAddr < Info.RegionBegin || BlockAddr >= Info.RegionEnd) in getInlineErrorInfo()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h148 MachineBasicBlock::iterator RegionBegin; variable
277 MachineBasicBlock::iterator begin() const { return RegionBegin; } in begin()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DPostRASchedulerList.cpp393 AntiDepBreak->BreakAntiDependencies(SUnits, RegionBegin, RegionEnd, in schedule()
666 RegionBegin = RegionEnd; in EmitSchedule()
683 RegionBegin = std::prev(RegionEnd); in EmitSchedule()
H A DMachineScheduler.cpp476 MachineBasicBlock::iterator RegionBegin; member
567 MachineBasicBlock::iterator I = R.RegionBegin; in scheduleRegions()
737 if (&*RegionBegin == MI) in moveInstruction()
738 ++RegionBegin; in moveInstruction()
748 if (RegionBegin == InsertPos) in moveInstruction()
749 RegionBegin = MI; in moveInstruction()
891 CurrentTop = nextIfDebug(RegionBegin, RegionEnd); in initQueues()
910 BB->splice(RegionBegin, BB, FirstDbgValue); in placeDebugValues()
911 RegionBegin = FirstDbgValue; in placeDebugValues()
919 if (&*RegionBegin == DbgValue) in placeDebugValues()
[all …]
H A DScheduleDAGInstrs.cpp188 RegionBegin = begin; in enterRegion()
200 ? &*skipDebugInstructionsBackward(RegionEnd, RegionBegin) in addSchedBarrierDeps()
564 for (MachineInstr &MI : make_range(RegionBegin, RegionEnd)) { in initSUnits()
792 for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin; in buildSchedGraph()
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsched-assert-onlydbg-value-empty-region.mir10 # BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&